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UT1553BRTR-GXC Datasheet

  • UT1553BRTR-GXC

  • Remote Terminal with RAM

  • 44頁

  • ETC

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UT1553B RTR Remote Terminal with RAM
F
EATURES
脣
Complete MIL-STD-1553B remote terminal interface
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1K x 16 of on-chip static RAM for message data,
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completely accessible to host
Self-test capability, including continuous loop-back
compare
Programmable memory mapping via pointers for
ef鏗乧ient use of internal memory, including buffering
multiple messages per subaddress
RT-RT Terminal Address Compare
Command word stored with incoming data for
enhanced data management
User selectable RAM Busy (RBUSY) signal for slow
or fast processor interfacing
Full military operating temperature range, -55擄C to
+125擄C, screened to the speci鏗乧 test methods listed in
脣
Table I of MIL-STD-883, Method 5004, Class B, also
Standard Military Drawing available
Available in 68-pin pingrid array package
I
NTRODUCTION
The UT1553B RTR is a monolithic CMOS VLSI solution
to the requirements of the dual-redundant MIL-STD-1553B
interface. Designed to reduce cost and space, the RTR
integrates the remote terminal logic with a user-con鏗乬ured
1K x 16 static RAM. In addition, the RTR has a 鏗俥xible
subsystem interface to permit use with most processors or
controllers.
The RTR provides all protocol, data handling, error
checking, and memory control functions, as well as
comprehensive self-test capabilities. The RTR鈥檚 memory
meets all of MIL-STD-1553B message storage needs
through user-de鏗乶ed memory mapping. This memory-
mapped architecture allows multiple message buffering at
MCSA(4:0)
MODE CODE/
SUBADDRESS
OUTPUT MULTIPLEXING AND
SELF-TEST WRAPAROUND LOGIC
OUT
RTA(4:0)
REMOTE TERMINAL
ADDRESS
CONTROL
INPUTS
STATUS
OUTPUTS
DECODER
COMMAND
RECOGNITION
CONTROL AND
ERROR LOGIC
1K X 16 RAM
ADDR(9:0)
MUX
ENCODER
PTR REGISTER
IN
OUT
DECODER
IN
12MHz
DATA(15:0)
2MHz
RESET
Figure 1. UT1553B RTR Functional Block Diagram
RTR-1

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