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UPSD3335B-24T6 Datasheet

  • UPSD3335B-24T6

  • Flash Programmable System Device with 8032 Microcontroller C...

  • 72.68KB

  • 8頁

  • STMICROELECTRONICS   STMICROELECTRONICS

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碌PSD3200
FAMILY
Flash Programmable System Device
with 8032 Microcontroller Core
DATA BRIEFING
FEATURES SUMMARY
s
The
碌PSD3200
Family combines a Flash PSD
architecture with an 8032 microcontroller core
The
碌PSD3200
Family of Flash PSDs features
dual banks of Flash memory, SRAM, general
purpose I/O and programmable logic, supervi-
sory functions and access via USB, I
2
C, ADC,
DDC and PWM channels, and an on-board
8032 microcontroller core, with two UARTs,
three 16-bit Timer/Counters and one External
Interrupt. As with other Flash PSD families, the
碌PSD3200
Family is also in-system program-
mable (ISP) via a JTAG ISP interface.
Large 8 KByte SRAM with battery back-up
option
Dual bank Flash memories
鈥?128 KByte or 256 KByte main Flash memory
鈥?32 KByte secondary Flash memory
s
Figure 1. Packages
s
s
TQFP52 (T)
Content Security
鈥?Block access to Flash memory
Programmable Decode PLD for flexible address
mapping of all memories.
High-speed clock standard 8032 core (12-cycle)
USB Interface (碌PSD3234A-40U6 only)
I
2
C interface for peripheral connections
Five Pulse Width Modulator (PWM) channels
Standalone Display Data Channel (DDC)
Six I/O ports with up to 50 I/O pins
3000 gate PLD with 16 macrocells
Supervisor functions
In-System Programming (ISP) via JTAG
Zero-Power Technology
Single Supply Voltage
鈥?4.5 to 5.5 V
鈥?3.0 to 3.6 V
TQFP80 (U)
s
s
s
s
s
s
s
s
s
s
s
s
June 2002
Complete data available on
Data-on-Disc CD-ROM
or at
www.st.com
.
1/8

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