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UPD98409GN-LMU Datasheet

  • UPD98409GN-LMU

  • ATM LIGHT SAR CONTROLLER

  • 398.02KB

  • 36頁

  • NEC   NEC

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DATA SHEET
MOS INTEGRATED CIRCUIT
碌
PD98409
ATM LIGHT SAR CONTROLLER
DESCRIPTION
The
碌
PD98409 (NEASCOT-S40C
TM
) is a high-performance SAR chip for segmentation and reassembly of ATM
cells. Provided with a PCI (Peripheral Component Interconnect) bus interface control memory and supporting a
MPEG packet transfer engine function to mitigate the workload of the CPU in transferring compressed image data,
this chip has ideal specifications for use in a set top box (STB) to interface with an ATM network. The
碌
PD98409
conforms to ATM Forum recommendations and has AAL5-SAR sublayer and ATM layer functions.
FEATURES
鈥?Conforms to ATM Forum
鈥?PCI bus interface (5/3.3 V, 32/64 bits, 33 MHz)
Conforms to PCI Local Bus Specification Revision 2.1
鈥?AAL-5 SAR sublayer and ATM layer functions
鈥?Hardware support of AAL-5 processing (non-AAL-5 processing can be supported in software)
鈥?Supports up to 64 virtual channels (VC) (64-VC control memory)
鈥?Two traffic shapers for transmission scheduling
鈥?MPEG packet transfer engine mitigating the workload of compressed image data transfer by CPU
鈥?Receive FIFO of 12 cells
鈥?PHY device I/F: UTOPIA Level-1 interface (octet/cell level handshake)
鈥?JTAG boundary scan test functions
鈥?0.35-
碌
m CMOS process, +5/+3.3-V power supply
- Bus interface +5 V : +5/+3.3-V power supply
- Bus interface +3.3 V : +3.3-V single power supply
ORDERING INFORMATION
Part Number
Package
240-pin plastic QFP (0.5-mm fine pitch) (32
脳
32 mm)
碌
PD98409GN-LMU
The information in this document is subject to change without notice.
Document No. S12775EJ2V0DS00 (2nd edition)
Date Published May 1998 N CP(K)
Printed in Japan
The mark
shows major revised points.
漏
1997, 1998

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