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UPD98401AGD-MML Datasheet

  • UPD98401AGD-MML

  • ATM SAR CHIP

  • 36頁

  • NEC   NEC

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DATA SHEET
MOS INTEGRATED CIRCUIT
碌
PD98401A
ATM SAR CHIP
DESCRIPTION
The
碌
PD98401A (NEASCOT-S15
TM
) is a high-performance SAR chip that segments and reassembles ATM cells.
This chip can interface with an ATM network when it is included in a workstation, computer, front-end processor,
network hub, or router. The
碌
PD98401A conforms to the ATM Forum Recommendation, and provides the functions
of the AAL-5 SAR sublayer and ATM layer.
The
碌
PD98401A is compatible with its predecessor,
碌
PD98401, in terms of hardware and software.
Functions are explained in detail in the following User鈥檚 Manual. Be sure to read this manual when designing your
system.
碌
PD98401A User鈥檚 Manual: S12054E
FEATURES
鈥?Conforms to ATM Forum
鈥?AAL-5 SAR sublayer and ATM layer functions
鈥?Hardware support of AAL-5 processing
鈥?Processing of non-AAL-5 traffic (AAL-3/4 cell, OAM cell, RM cell) by software with raw cell processing function
鈥?Hardware support of comparison/generation of CRC-10 for non-AAL-5 traffic
鈥?Supports up to 32K virtual channels (VC)
鈥?Provided with 16 traffic shapers that carry out transmission scheduling (control of average rate/peak rate) so as to
set different transmission rate for each VC
鈥?Interface and commands for controlling PHY device
鈥?Employs 鈥淯TOPIA interface鈥?as cell data interface with PHY device
- Octet-level handshake
- Cell-level handshake
鈥?32-bit general-purpose bus interface
鈥?High-speed DMAC (supports 1-, 2-, 4-, 8-, 12-, and 16-word burst)
鈥?JTAG boundary scan test function (IEEE1149.1)
鈥?CMOS technology
鈥?+5 V single power source
Remark
In this document, an active low pin is indicated by
脳脳脳_B
(_B after a pin name).
The information in this document is subject to change without notice.
Document No. S12100EJ3V0DS00 (3rd edition)
Date Published February 1999 N CP(K)
Printed in Japan
The mark
shows major revised points.
漏
1997

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