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DATA SHEET

MOS INTEGRATED CIRCUIT

碌

PD72107

LAP-B CONTROLLER

Link Access Procedure Balanced mode

The

碌

PD72107 is an LSI that supports LAP-B protocol specified by the ITU-T recommended X.25 on a single

chip.

FEATURES

鈥?Complied with ITU-T recommended X.25 (LAP-B84

edition)

HDLC frame control

Sequence control

Flow control

鈥?ITU-T recommended X.75 supported

鈥?TTC standard JT-T90 supported

鈥?Optional functions

Option frame

Global address frame

Error check deletion frame

鈥?Powerful test functions

Data loopback function

Loopback test link function

Frame trace function

鈥?Abundant statistical information

鈥?Detailed mode setting function

鈥?Modem control function

鈥?On-chip DMAC (Direct Memory Access Controller)

24-bit address

Byte/word transfer enabled (switch with external pin)

鈥?Memory-based interface

Memory-based command

Memory-based status

Memory-based transmit/receive data

鈥?MAX.4 Mbps serial transfer rate

鈥?NRZ, NRZI coding

ORDERING INFORMATION

Part Number

Package

64-pin plastic shrink DIP (750 mils)

80-pin plastic QFP (14 x 14 mm)

68-pin plastic QFJ (950 x 950 mils)

碌

PD72107CW

碌

PD72107GC-3B9

碌

PD72107L

The information in this document is subject to change without notice.

Document No. S12962EJ5V0DS00 (5th edition)

Date Published October 1998 N CP(K)

Printed in Japan

漏

1998

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