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UPD720101GJ-UEN Datasheet

  • UPD720101GJ-UEN

  • USB2.0 HOST CONTROLLER

  • 36頁

  • NEC   NEC

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DATA SHEET
MOS INTEGRATED CIRCUIT
碌
PD720101
USB2.0 HOST CONTROLLER
The
碌
PD720101 complies with the Universal Serial Bus Specification Revision 2.0 and Open Host Controller
Interface Specification for full-/low-speed signaling and Intel's Enhanced Host Controller Interface Specification for
high-speed signaling and works up to 480 Mbps. The
碌
PD720101 is integrated 3 host controller cores with PCI
interface and USB2.0 transceivers into a single chip.
Detailed function descriptions are provided in the following user鈥檚 manual. Be sure to read the manual before designing.
碌
PD720101 User鈥檚 Manual: S16336E
FEATURES
鈥?Compliant with Universal Serial Bus Specification Revision 2.0 (Data rate 1.5/12/480 Mbps)
鈥?Compliant with Open Host Controller Interface Specification for USB Rev 1.0a
鈥?Compliant with Enhanced Host Controller Interface Specification for USB Rev 1.0
鈥?PCI multi-function device consists of two OHCI host controller cores for full-/low-speed signaling and one EHCI host
controller core for high-speed signaling.
鈥?Root hub with 5 (max.) downstream facing ports which are shared by OHCI and EHCI host controller cores.
鈥?All downstream facing ports can handle high-speed (480 Mbps), full-speed (12 Mbps), and low-speed (1.5 Mbps)
transaction.
鈥?Configurable number of downstream facing ports (2 to 5)
鈥?32-bit 33 MHz host interface compliant to PCI Specification release 2.2
鈥?Supports PCI Mobile Design Guide Revision 1.1
鈥?Supports PCI-Bus Power Management Interface Specification release 1.1
鈥?PCI bus bus-master access
鈥?System clock is generated by 30 MHz X鈥檛al or 48 MHz clock input.
鈭?/div>
System clock frequency should be set from system software (BIOS) or EEPROM. More detail, see
碌
PD720101
User鈥檚 Manual.
鈥?Operational registers direct-mapped to PCI memory space
鈥?Legacy support for all downstream facing ports. Legacy support features allow easy migration for motherboard
implementation.
鈥?3.3 V power supply, PCI signal pins have 5 V tolerant circuit.
ORDERING INFORMATION
Part Number
Package
144-pin plastic LQFP (Fine pitch) (20
脳
20)
144-pin plastic FBGA (12
脳
12)
碌
PD720101GJ-UEN
碌
PD720101F1-EA8
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all products and/or types are available in every country. Please check with an NEC Electronics
sales representative for availability and additional information.
Document No. S16265EJ4V0DS00 (4th edition)
Date Published June 2004 NS CP (N)
Printed in Japan
The mark
shows major revised points.
2002

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