鈥?/div>
DRAM and pseudo SRAM refreshing functions
DMA controller : 2 channels
16-bit timer : 2 channels
Time base counter
On-chip clock generator
Programmable wait function
Standby function (STOP/HALT)
The information in this document is subject to change without notice.
Document No. U10090EJ8V0DS00 (8th edition)
Date Published November 1997 N
Printed in Japan
The mark
shows major revised points.
漏
1996
1995