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UPD45128841G5-A75 Datasheet

  • UPD45128841G5-A75

  • 128M-bit Synchronous DRAM 4-bank, LVTTL

  • 92頁

  • NEC   NEC

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DATA SHEET
MOS INTEGRATED CIRCUIT
碌
PD45128441, 45128841, 45128163
128M-bit Synchronous DRAM
4-bank, LVTTL
Description
The
碌
PD45128441, 45128841, 45128163 are high-speed 134,217,728-bit synchronous dynamic random-access
memories, organized as 8,388,608
脳
4
脳
4, 4,194,304
脳
8
脳
4, 2,097,152
脳
16
脳
4 (word
脳
bit
脳
bank), respectively.
The synchronous DRAMs achieved high-speed data transfer using the pipeline architecture.
All inputs and outputs are synchronized with the positive edge of the clock.
The synchronous DRAMs are compatible with Low Voltage TTL (LVTTL).
These products are packaged in 54-pin TSOP (II).
Features
鈥?/div>
Fully Synchronous Dynamic RAM, with all signals referenced to a positive clock edge
鈥?/div>
Pulsed interface
鈥?/div>
Possible to assert random column address in every cycle
鈥?/div>
Quad internal banks controlled by BA0(A13) and BA1(A12)
鈥?/div>
Byte control (脳16) by LDQM and UDQM
鈥?/div>
Programmable Wrap sequence (Sequential / Interleave)
鈥?/div>
Programmable burst length (1, 2, 4, 8 and full page)
鈥?/div>
Programmable /CAS latency (2 and 3)
鈥?/div>
Automatic precharge and controlled precharge
鈥?/div>
CBR (Auto) refresh and self refresh
鈥?脳4, 脳8, 脳16
organization
鈥?/div>
Single 3.3 V
鹵
0.3 V power supply
鈥?/div>
LVTTL compatible inputs and outputs
鈥?/div>
4,096 refresh cycles / 64 ms
鈥?/div>
Burst termination by Burst stop command and Precharge command
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
Document No. M12650EJBV0DS00 (11th edition)
Date Published April 2000 NS CP (K)
Printed in Japan
The mark
鈥?/div>
shows major revised points.
漏
1997

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