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UPD44323362F1-C40-FJ1 Datasheet

  • UPD44323362F1-C40-FJ1

  • 32M-BIT CMOS SYNCHRONOUS FAST STATIC RAM 1M-WORD BY 36-BIT H...

  • 250.35KB

  • 28頁

  • NEC   NEC

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DATA SHEET
MOS INTEGRATED CIRCUIT
碌
PD44323362
32M-BIT CMOS SYNCHRONOUS FAST STATIC RAM
1M-WORD BY 36-BIT
HSTL INTERFACE / REGISTER-REGISTER / LATE WRITE
Description
The
碌
PD44323362 is a 1,048,576 words by 36 bits synchronous static RAM fabricated with advanced CMOS
technology using Full-CMOS six-transistor memory cell.
The
碌
PD44323362 is suitable for applications which require high-speed, low voltage, high-density memory and wide
bit configuration, such as cache and buffer memory.
The
碌
PD44323362 is packaged in a 119-pin PLASTIC BGA (Ball Grid Array).
Features
鈥?/div>
Fully synchronous operation
鈥?/div>
HSTL Input / Output levels
鈥?/div>
Fast clock access time: 2.0 ns / 250 MHz
鈥?/div>
Asynchronous output enable control: /G
鈥?/div>
Byte write control: /SBa (DQa1 to DQa9), /SBb (DQb1 to DQb9), /SBc (DQc1 to DQc9), /SBd (DQd1 to DQd9)
鈥?/div>
Common I/O using three-state outputs
鈥?/div>
Internally self-timed write cycle
鈥?/div>
Late write with 1 dead cycle between Read-Write
鈥?/div>
User-configurable outputs: Controlled impedance outputs or push-pull outputs
鈥?/div>
Boundary scan (JTAG) IEEE 1149.1 compatible
鈥?/div>
2.5
鹵
0.125 V (Chip) / 1.4 to 1.9 V (I/O) supply
鈥?/div>
119 bump BGA package, 1.27 mm pitch, 14 mm
脳
22 mm
鈥?/div>
Sleep mode: ZZ (Enables sleep mode, active high)
Ordering Information
Part number
Access time
2.0 ns
Clock frequency
250 MHz
Package
119-pin PLASTIC BGA
碌
PD44323362F1-C40-FJ1
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all products and/or types are available in every country. Please check with an NEC Electronics
sales representative for availability and additional information.
Document No. M16379EJ4V0DS00 (4th edition)
Date Published May 2004 NS CP(K)
Printed in Japan
The mark
shows major revised points.
2002

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