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UPD44165084F5-E40-EQ1 Datasheet

  • UPD44165084F5-E40-EQ1

  • 18M-BIT QDRII SRAM 4-WORD BURST OPERATION

  • 32頁

  • NEC   NEC

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DATA SHEET
MOS INTEGRATED CIRCUIT
碌
PD44165084, 44165184, 44165364
18M-BIT QDR
TM
II SRAM
4-WORD BURST OPERATION
Description
The
碌
PD44165084 is a 2,097,152-word by 8-bit, the
碌
PD44165184 is a 1,048,576-word by 18-bit and the
碌
PD44165364 is a 524,288-word by 36-bit synchronous quad data rate static RAM fabricated with advanced CMOS
technology using full CMOS six-transistor memory cell.
The
碌
PD44165084,
碌
PD44165184 and
碌
PD44165364 integrates unique synchronous peripheral circuitry and a
burst counter. All input registers controlled by an input clock pair (K and /K) are latched on the positive edge of K and
/K.
These products are suitable for application which require synchronous operation, high speed, low voltage, high
density and wide bit configuration.
These products are packaged in 165-pin PLASTIC BGA.
Features
鈥?/div>
1.8 鹵 0.1 V power supply and HSTL I/O
鈥?/div>
DLL circuitry for wide output data valid window and future frequency scaling
鈥?/div>
Separate independent read and write data ports with concurrent transactions
鈥?/div>
100% bus utilization DDR READ and WRITE operation
鈥?/div>
Four-tick burst for reduced address frequency
鈥?/div>
Two input clocks (K and /K) for precise DDR timing at clock rising edges only
鈥?/div>
Two output clocks (C and /C) for precise flight time
and clock skew matching-clock and data delivered together to receiving device
鈥?/div>
Internally self-timed write control
鈥?/div>
Clock-stop capability with
碌
s restart
鈥?/div>
User programmable impedance output
鈥?/div>
Fast clock cycle time : 4.0 ns (250 MHz) , 5.0 ns (200 MHz) , 6.0 ns (167 MHz)
鈥?/div>
Simple control logic for easy depth expansion
鈥?/div>
JTAG boundary scan
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all products and/or types are available in every country. Please check with an NEC Electronics
sales representative for availability and additional information.
Document No. M15825EJ7V1DS00 (7th edition)
Date Published
July
2004 NS CP(K)
Printed in Japan
The mark
shows major revised points.
2001

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