V
R
5432
64-Bit MIPS
RISC Microprocessor
Description
The V
R
5432鈩?microprocessor brings a new level of high-end performance to low-cost
embedded design. This member of NEC鈥檚 V
R
Series鈩?microprocessors operates at either
167 or 200 MHz and uses a gated clock, minimal switching techniques, and a special circuit
design to keep power consumption low. Its symmetric dual-issue pipeline with six
independent execution units executes any combination of arithmetic logic unit (ALU), floating-
point, or rotate instructions, while 32 KB instruction and data caches implement cache line
locking to keep critical code and data cached. Multiple outstanding read transactions allow
both caches to be filled concurrently, keeping the processor supplied with a steady stream of
instructions and data. Mapping of accesses to virtual memory addresses is optimized with a
48-double-entry joint instruction/data translation lookaside buffer (TLB) and two separate
four-entry micro TLBs for instructions and data.
Applications
Features
Digital set-top boxes, Internet appliances, and office automation equipment
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Dual-issue superscalar pipeline with six independent units
Separate 32 KB two-way, set-associative instruction and data caches with cache line
locking and parity
Two unified 64-bit integer/floating-point units, each with 64-bit barrel shifters
High-speed operating frequency
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316 Dhrystone MIPS at 167 MHz
377 Dhrystone MIPS at 200 MHz
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32-bit system bus
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83 MHz SysAD bus speed at 167 MHz
100 MHz SysAD bus speed at 200 MHz
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On-chip debugging via JTAG, N-wire and N-trace functions
Low power consumption
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1.8 watts at 167 MHz (typ.)
2.1 watts at 200 MHz (typ.)
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64-bit architecture with a 32-bit multiplexed address/data bus interface
MIPS IV-compliant instruction set architecture
MIPS architecture extensions
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Integer multiply-accumulate instructions and other register-based multiply variations
for fast DSP support
Integer rotate instructions for fast 32-bit and 64-bit string operations
Packed data vector operations for fast 8 x 8-bit image and multimedia processing
Cache line locking instructions (both caches) for better cache management
UPD30541GD-167-WML相關(guān)型號PDF文件下載
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英文版
ETC
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英文版
ETC
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英文版
ETC
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ETC
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英文版
CCD, SINGLE BOARD COLOR IMAGE SENSOR
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UPD3570 2560-BIT CCD LINEAR IMAGE SENSOR
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UPD3570 2560-BIT CCD LINEAR IMAGE SENSOR
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5000 BIT CCD LINEAR IMAGE SENSOR
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5000 BIT CCD LINEAR IMAGE SENSOR
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2048-BIT CCD LINEAR IMAGE SENSOR
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2048-BIT CCD LINEAR IMAGE SENSOR
NEC [NEC]
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2592-BIT CCD LINEAR IMAGE SENSOR
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2592-BIT CCD LINEAR IMAGE SENSOR
NEC [NEC]
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1024 BIT LINEAR IMAGE SENSOR
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1024 BIT LINEAR IMAGE SENSOR
NEC [NEC]
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10600 PIXELS x 3 COLOR CCD LINEAR IMAGE SENSOR
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英文版
10600 PIXELS x 3 COLOR CCD LINEAR IMAGE SENSOR
NEC [NEC]
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英文版
LINEAR CCD IMAGE ARRAY,3 VERT PIXELS,2.7K HORIZ PIXELS,DIP
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