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UPD30200GD-100-MBB Datasheet

  • UPD30200GD-100-MBB

  • 64-Bit Microprocessor

  • 24頁

  • ETC

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DATA SHEET
碌
PD30200, 30210
V
R
4300
TM
, V
R
4305
TM
, V
R
4310
TM
64-BIT MICROPROCESSOR
MOS INTEGRATED CIRCUIT
DESCRIPTION
The
碌
PD30200-100, 30200-133 (V
R
4300), 30200-80 (V
R
4305), and 30210 (V
R
4310) are high-performance, 64-
bit RISC (Reduced Instruction Set Computer) type V
R
Series
TM
microprocessors employing the RISC architecture
developed by MIPS
TM
Technologies Inc.
The V
R
4300, V
R
4305, and V
R
4310 are intended for the high-performance embedded device field and have 32-
bit system interface buses.
Detailed function descriptions are provided in the following user鈥檚 manual. Be sure to read this
manual before designing.
鈥?V
R
4300, V
R
4305, V
R
4310 User鈥檚 Manual (U10504E)
FEATURES
鈥?/div>
Employs 64-bit RISC MIPS architecture
鈥?/div>
High-speed operation processing
鈥?5-stage pipeline processing
鈥?High-speed execution of integer and floating-point operations
鈥?48 SPECint92, 36 SPECfp92, 106 MIPS, at 80 MHz operation (
碌
PD30200-80)
60 SPECint92, 45 SPECfp92, 131 MIPS, at 100 MHz operation (
碌
PD30200-100)
80 SPECint92, 60 SPECfp92, 177 MIPS at 133 MHz operation (
碌
PD30200-133,
碌
PD30210-133)
100 SPECint92, 75 SPECfp92, 221 MIPS at 167 MHz operation (
碌
PD30210-167)
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
Instruction set compatible with V
R
4000
TM
Series (conforms to MIPS-I/II/III)
On-chip cache memory (Instruction: 16 Kbytes, Data: 8 Kbytes)
32-bit address/data multiplexed bus facilitating system design
Low power consumption
鈥?/div>
碌
PD30200-80: 1.5 W (TYP.) (at 80 MHz operation)
鈥?/div>
碌
PD30200-100, 30200-133: 1.8 W (TYP.) (at 100 MHz operation), 2.4 W (TYP.) (at 133 MHz operation)
鈥?/div>
碌
PD30210-脳脳脳: 1.9 W (TYP.) (at 133 MHz operation), 2.4 W (TYP.) (at 167 MHz operation)
鈥?/div>
Supply voltage: 3.3
鹵
0.3 V (
碌
PD30200-80, 30200-100), 3.0 to 3.5 V (
碌
PD30200-133, 30210-脳脳脳)
Unless otherwise specified, the V
R
4300 (
碌
PD30200) is treated as the representative model throughout this document.
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for availability
and additional information.
Document No. U10116EJ7V0DS00 (7th edition)
Date Published November 2000 N CP(K)
Printed in Japan
The mark
shows major revised points.
漏
1995, 1998
1994

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