DATA SHEET
碌
PD178023,178024
8-BIT SINGLE-CHIP MICROCONTROLLER
MOS INTEGRATED CIRCUIT
DESCRIPTION
The
碌
PD178023, 178024 are 8-bit single-chip CMOS microcontrollers containing hardware for digital tuning
systems.
These microcontrollers employ a 78K/0 series architecture CPU and allow easy access to internal memories at
high speed and easy control of peripheral hardware units. The high-speed 78K/0 series instructions are ideal for
system control.
As peripheral hardware, a prescaler, PLL frequency synthesizer, and frequency counter for digital tuning systems
are provided, as well as many I/O ports, timers, A/D converter, serial interface, and a power-ON clear circuit.
In addition, three serial interfaces, I
2
C bus (IIC0), three-wire (SIO3), and UART are provided.
Moreover, a flash memory model, the
碌
PD178F124, that operates in the same supply voltage range as the mask
ROM models, and various development tools are also under development.
For the detailed functional description, refer to the following User鈥檚 Manuals:
碌
PD178024, 178124 Subseries User鈥檚 Manual : U13915E
78K/0 Series User鈥檚 Manual - Instruction
: U12326E
FEATURES
鈥?/div>
High-capacity ROM and RAM
Item
Part Number
Program Memory (ROM)
Data Memory
Internal high-speed RAM
24K bytes
32K bytes
1024 bytes
碌
PD178023
碌
PD178024
鈥?/div>
Instruction cycle:
f
X
= 4.5 MHz)
0.45/0.89/1.78/3.56/7.11
碌
s (with crystal resonator of
鈥?/div>
Hardware for PLL frequency synthesizer
鈥?/div>
Vectored interrupt sources:
鈥?/div>
Supply voltage
phase comparator, charge pump
17
Dual modulus prescaler, programmable divider,
鈥?/div>
Many internal hardware units
General-purpose I/O ports, A/D converter, serial
interface (I
2
C bus and UART mode), timers, frequency
:V
DD
= 4.5 to 5.5 V (during PLL and CPU
operations)
counter, power-ON clear circuit
:V
DD
= 3.5 to 5.5 V (during CPU operation)
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for availability
and additional information.
Document No. U14126EJ1V0DS00 (1st edition)
Date Published September 1999 N CP(K)
Printed in Japan
漏
1999
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