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UPD178004AGC Datasheet

  • UPD178004AGC

  • 8-BIT SINGLE-CHIP MICROCONTROLLERS

  • 308.85KB

  • 56頁

  • NEC   NEC

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DATA SHEET
MOS INTEGRATED CIRCUIT
碌
PD178004A, 178006A, 178016A, 178018A
8-BIT SINGLE-CHIP MICROCONTROLLERS
The
碌
PD178004A, 178006A, 178016A and 178018A are 8-bit single-chip CMOS microcontrollers that incorporate
hardware for digital tuning systems.
The CPU uses the 78K/0 architecture, which makes it easy to implement high-speed access to internal memory
and control of peripheral hardware. Also, the instructions used are the high-speed 78K/0 instructions, suitable for
system control.
The rich assortment of peripheral hardware includes an input/output port, 8-bit timer, A/D converter, serial interface,
power-ON clear circuits, as well as a pre-scaler for digital tuning, a PLL frequency synthesizer and a frequency counter.
The
碌
PD178P018A, one-time PROM or EPROM versions which can be operated in the same supply voltage range
as for the mask ROM versions, and various development tools, are also available.
For more information on functions, refer to the following User鈥檚 Manuals. Be sure to read them when
designing.
碌
PD178018A Subseries User鈥檚 Manual: to be prepared
78K/0 Series User鈥檚 Manual Instruction: U12326E
FEATURES
鈥?Internal high-capacity ROM and RAM
Items
Product Name
Program Memory
ROM
32 Kbytes
48 Kbytes
2 048 bytes
60 Kbytes
Internal High-Speed RAM
1 024 bytes
Data Memory
Buffer RAM
32 bytes
Internal Expanded RAM
Not provided
碌
PD178004A
碌
PD178006A
碌
PD178016A
碌
PD178018A
鈥?Instruction Cycle: 0.44
碌
s (4.5-MHz crystal oscillator used)
鈥?Large array of on-chip peripheral hardware
General-purpose input/output port, A/D converter, serial interface, timer, frequency counter, power-ON clear
circuits.
鈥?On-chip hardware for a PLL frequency synthesizer.
Dual modulus pre-scaler, programmable divider, phase comparator, charge pump.
鈥?Vector interrupt sources: 17
鈥?Supply Voltage: V
DD
= 4.5 to 5.5 V (during PLL operation)
V
DD
= 3.5 to 5.5 V (during CPU operation, when the system clock is f
X
/2 or lower)
V
DD
= 4.5 to 5.5 V (during CPU operation, when the system clock is f
X
)
The information in this document is subject to change without notice.
Document No. U12641EJ1V0DS00 (1st Edition)
Date Published July 1997 N
Printed in Japan
漏
1997

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