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UPC4093G2 Datasheet

  • UPC4093G2

  • J-FET INPUT LOW-OFFSET OPERATIONAL AMPLIFIER

  • 12頁

  • NEC   NEC

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DATA SHEET
BIPOLAR ANALOG INTEGRATED CIRCUIT
碌
PC4093
J-FET INPUT LOW-OFFSET OPERATIONAL AMPLIFIER
The
碌
PC4093 operational amplifier is a high-speed version of the
碌
PC4091. NEC's unique high-speed PNP
transistor (f
T
= 300 MHz) in the output stage realizes a high slew rate of 25 V/
碌
s under voltage-follower conditions
without an oscillation problem. Zener-zap resistor trimming in the input stage produces excellent offset voltage and
temperature drift characteristics.
With AC performance characteristics that are two times better than conventional bi-FET operation amplifiers, the
碌
PC4093 is ideal for fast integrators, active filters, and other high-speed circuit applications.
FEATURES
鈥?Stable operation with 220 pF capacitive load
鈥?Low input offset voltage and offset voltage null
capability
鹵2.5
mV (MAX.)
鹵7
碌
V/擄C (TYP.) temperature drift
鈥?Very low input bias and offset currents
鈥?Low noise : e
n
= 19 nV/
鈭欻z
(TYP.)
鈥?Output short circuit protection
鈥?High input impedance ... J-FET Input Stage
鈥?Internal frequency compensation
鈥?High slew rate: 25 V/
碌
s (TYP.)
ORDERING INFORMATION
Part Number
Package
8-pin plastic DIP (300 mil)
8-pin plastic SOP (225 mil)
碌
PC4093C
碌
PC4093G2
EQUIVALENT CIRCUIT
V
+
(7)
Q
9
(2)
I
I
Q
1
I
N
(3)
Q
5
(1)
OFFSET
NULL
Q
3
Q
4
(5)
OFFSET
NULL
Q
2
C
1
D
1
Q
10
Q
7
(6)
HIGH SPEED
PNP
Q
6
OUT
PIN CONFIGURATION
(Top View)
碌
PC4093C, 4093G2
OFFSET
1
NULL
I
I
2
鈭?/div>
+
8 NC
7 V
+
I
N
V
鈭?/div>
3
6 OUT
OFFSET
NULL
4
5
Q
8
(4)
Remark
NC : No Connection
V
鈥?/div>
TRIMMED
The information in this document is subject to change without notice.
Document No. G13906EJ1V0DS00 (1st edition)
Date Published December 1998 N CP(K)
Printed in Japan
漏
1998

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