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UPA1500BH Datasheet

  • UPA1500BH

  • N-CHANNEL POWER MOS FET ARRAY SWITCHING USE

  • 8頁

  • NEC   NEC

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DATA SHEET
COMPOUND FIELD EFFECT POWER TRANSISTOR
PA1500B
N-CHANNEL POWER MOS FET ARRAY
SWITCHING USE
DESCRIPTION
The
PA1500B is N-channel Power MOS FET Array
that built in 4 circuits and surge absorber designed for
solenoid, motor and lamp driver.
PACKAGE DIMENSIONS
(in millimeters)
31.5 MAX.
4.2 MAX.
鈥?4 V driving is possible
鈥?Large Current and Low On-state Resistance
I
D(DC)
=
鹵3
A
R
DS(on)1
鈮?/div>
0.18
鈩?/div>
MAX. (V
GS
= 10 V, I
D
= 2 A)
R
DS(on)2
鈮?/div>
0.24
鈩?/div>
MAX. (V
GS
= 4 V, I
D
= 2 A)
鈥?Low Input Capacitance Ciss = 200 pF TYP.
鈥?Surge Absorber, built in
1 2 3 4 5 6 7 8 9 10 11 12
2.54 TYP.
0.7鹵0.1
1.4鹵0.1 0.5鹵0.1
10.0 MIN.
10.5 MAX.
2.5 TYP.
FEATURES
1.4 TYP.
ORDERING INFORMATION
Type Number
Package
12 Pin SIP
ELECTRODE CONNECTION
1, 5, 8, 12 GATE
2, 4, 9, 11 DRAIN, ANODE
6, 7
3, 10
SOURCE
CATHODE
PA1500BH
CONNECTION DIAGRAM
ABSOLUTE MAXIMUM RATINGS (T
A
= 25 藲C)
Drain to Source Voltage
V
DSS
Note 1
60
Note 2
Gate to Source Voltage
V
GSS
鹵20
Drain Current (DC)
I
D(DC)
鹵3.0
Note 3
Drain Current (pulse)
I
D(pulse)
鹵12
Note 4
Repetitive peak Reverse Voltage V
RRM
65
Note 4
Diode Forward Current
I
F(av)
3.0
Note 5
Total Power Dissipation
P
T1
28
Note 6
Total Power Dissipation
P
T2
4.0
Channel Temperature
T
CH
150
Storage Temperature
T
stg
鈥?5 to 150
Note 7
Single Avalanche Current
I
AS
3.0
Note 7
Single Avalanche Energy
E
AS
0.9
Notes 1.
V
GS
= 0
2.
V
DS
= 0
3.
PW
鈮?/div>
10
s, Duty Cycle
鈮?/div>
1 %
4.
Rating of Surge Absorber
5.
4 Circuits, T
C
= 25 藲C
6.
4 Circuits, T
A
= 25 藲C
7.
Starting T
CH
= 25 藲C, V
DD
= 30 V, V
GS
= 20
R
G
= 25
鈩?
L = 100
H
V
V
A/unit
A/unit
V
A/unit
W
W
C
C
A
mJ
2
D
5
3
D
6
4
R
G
1
6
Z
D
9
D
1
5
R
G
Z
D
10
11
D
8
D
2
D
7
R
G
8
Z
D
D
3
12
R
G
Z
D
D
4
7
V
鈫?/div>
0,
D
1
to D
4
D
5
to D
8
Z
D
R
G
:
:
:
:
Body Diode
Surge Absorber
Gate to Source Protection Diode
Gate Input Resistance 330
鈩?/div>
TYP.
The diode connected between the gate and source of the transistor serves as a protector against ESD. When this
device is actually used, an additional protection circuit is externally required if a voltage exceeding the rated voltage
may be applied to this device.
Document No. G10597EJ2V0DS00 (2nd edition)
Date Published December 1995 P
Printed in Japan
1995

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