鈥?/div>
EXCELLENT FOR ANALOG ADDITIONS & FORMATION OF 2-INPUT OR/NOR GATES
DESCRIPTION AND APPLICATIONS
The
碌
PA104 is a user-configurable, Si bipolar transistor array for formation of high speed OR/NOR gates. Its
internal transistor configuration and external connection options allow the user considerable flexibility in its
application. Its high gain bandwidth product (f
T
= 9 GHz) make it applicable for electro-optical, signal processing,
cellular telephone systems, instrumentation, and high speed gigabit logic circuits.
ORDERING INFORMATION
PART NUMBER
PACKAGE
14-pin ceramic package
14-pin plastic SOP (225 mil)
碌
PA104B-E1
碌
PA104G-E1
ABSOLUTE MAXIMUM RATINGS (T
A
= +25
擄
C)
SYMBOLS
V
CBO
*
V
CEO
*
V
EBO
*
I
C
*
P
T
PARAMETERS
Collector to Base Voltage
Collector to Emitter Voltage
Emitter to Base Voltage
Collector Current
Power Dissipation
碌
PA104B
碌
PA104G
Junction Temperature
碌
PA104B
碌
PA104G
Storage Temperature
碌
PA104B
碌
PA104G
UNITS
V
V
V
mA
mW
mW
擄C
擄C
擄C
擄C
RATINGS
15
6
2.5
40
650
350
200
125
鈥?5 to +200
鈥?5 to +125
T
J
T
STG
*
Absolute maximum ratings for each transistor.
Caution electro-static sensitive devices
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for availability
and additional information.
Document No. P10709EJ2V0DS00 (2nd edition)
Date Published October 1999 N CP(K)
Printed in Japan
The mark
shows major revised points.
漏
1995, 1999