鈥?/div>
TWO PACKAGE OPTIONS:
碌
PA103B:
Superior thermal dissipation due to studded ceramic package
碌
PA103G:
Reduced circuit size due to 14-pin plastic SOP package for surface mounting
DESCRIPTION AND APPLICATIONS
The
碌
PA103 is a user configurable Silicon bipolar transistor array consisting of a common emitter pair and three
individual bipolar transistors. It is available in a surface mount 14-pin plastic SOP package and a 14-pin ceramic package.
Typical applications include: differential amplifiers and oscillators, high speed comparators, advanced cellular phone
systems, electro-optic and other signal processing up to 1.5 gigabits/second.
ORDERING INFORMATION
PART NUMBER
PACKAGE
14-pin ceramic package
14-pin plastic SOP (225 mil)
碌
PA103B-E1
碌
PA103G-E1
ABSOLUTE MAXIMUM RATINGS (T
A
= +25
擄
C)
SYMBOLS
V
CBO
*
V
CEO
*
V
EBO
*
I
C
*
P
T
PARAMETERS
Collector to Base Voltage
Collector to Emitter Voltage
Emitter to Base Voltage
Collector Current
Power Dissipation
碌
PA103B
碌
PA103G
Junction Temperature
碌
PA103B
碌
PA103G
Storage Temperature
碌
PA103B
碌
PA103G
UNITS
V
V
V
mA
mW
mW
擄C
擄C
擄C
擄C
RATINGS
15
6
2.5
40
650
350
200
125
鈥?5 to +200
鈥?5 to +125
T
J
T
STG
*
Absolute maximum ratings for each transistor.
Caution electro-static sensitive devices
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for availability
and additional information.
Document No. P10708EJ2V0DS00 (2nd edition)
Date Published October 1999 N CP(K)
Printed in Japan
The mark
shows major revised points.
漏
1995, 1999
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