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UD61466DC08 Datasheet

  • UD61466DC08

  • x4 Static Column Mode DRAM

  • 14頁(yè)

  • ETC

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Maintenance only
Features
UD61466
64K x 4 DRAM
SCM facilitates faster data operation
with predefined row address. Via 8
address inputs the 16 address bits
are transmitted into the internal
address memories in a time-multi-
plex operation. The falling RAS-
edge takes over the row address.
After the row address hold time the
column address can be applied.
During the Read cycle the address
transfer is not latched by the falling
edge at the CAS input, so that the
column address must be applied
until the data are valid at the output.
During Write the column address is
taken over with the falling edge of
the control signal CAS, or W, that
becomes active as the last. The sel-
ection of one or more memory cir-
cuits can be made via the RAS
input.
Data Output Control
The usual state of the data output is
the High-Z state. Whenever CAS is
inactive (HIGH), Q will float (High-Z).
Thus, CAS functions as data output
control.
After access time, in case of a Read
cycle, the output is activated, and it
contains the logic 鈥?鈥?or 鈥?鈥?
The memory cycle being a Read,
Read-Write or a Write cycle (W-con-
trolled), Q changes from High-Z
state to the active state (鈥?鈥?or 鈥?鈥?.
After access time, the contents of
the selected cell will be available,
with the exception of the Write cycle.
The output remains active until CAS
becomes inactive, irrespective of
RAS becoming inactive or not. The
memory cycle being a Write cycle
(CAS-controlled), the data output
keeps its High-Z state throughout
the whole cycle. This configuration
makes Q fully controllable by the
user merely through the timing of W.
The output storaging the data, they
remain valid from the end of access
time until the start of another cycle.
F
Dynamic random access memory
F
F
F
F
F
F
F
F
F
F
F
65536 x 4 bits manufactured
using a CMOS technology
RAS access times 70 ns/80 ns
TTL-compatible
Three-state outputs bidirectional
256 refresh cycles
4 ms refresh cycle time
STATIC COLUMN MODE
Operating modes: Read, Write,
Read - Write,
RAS only Refresh,
Hidden Refresh with address
transfer
Low power dissipation
Power supply voltage 5 V
Package PDIP18 (300 mil)
Operating temperature range
0 to 70 擄C
Quality assessment according to
CECC 90000, CECC 90100 and
CECC 90112
Read-Write-Control
The choice between Read or Write
cycle is made at the W input. HIGH
at the W input causes a Read cycle,
Description
meanwhile LOW leads to a Write
cycle.
Addressing
The UD61466 is a dynamic random Both CAS-controlled and W-control-
access memory organized 65536 led Write cycles are possible with
words by 4 bits.
activated RAS signal.
Pin Configuration
Pin Description
(OE)
G
DQ0
DQ1
1
2
3
4
5
6
7
8
9
18
17
16
15
13
12
11
10
VSS
DQ3
CAS
DQ2
A6
A3
A4
A5
A7
Signal Name
A0 - A7
DQ0 - DQ3
W
RAS
G
VCC
VSS
CAS
Signal Description
Address Inputs
Data In/Out
Read, Write Control
Row Address Strobe
Output Enable
Power Supply Voltage
Ground
Column Address Strobe
(WE)
W
RAS
A0
A2
A1
VCC
PDIP
14
SOJ
Top View
December 12, 1997
1

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