Maintenance only
FPM facilitates faster data operation
with predefined row address. Via 8
address inputs the 16 address bits
Dynamic random access memory
are transmitted into the internal
65536 x 4 bits manufactured
address memories in a time-multi-
using a CMOS technology
plex operation. The falling RAS-
RAS access times 70 ns/80 ns
edge takes over the row address.
TTL-compatible
Three-state outputs bidirectional After the row address hold time the
column address can be applied. The
256 refresh cycles
bit pattern that is available at the
4 ms refresh cycle time
address outputs during the set-up
FAST PAGE MODE
time and after the falling edge of
Operating modes: Read, Write,
CAS is interpreted as row address.
Read - Write,
During Write the column address is
RAS only Refresh,
taken over with the falling edge of
Hidden Refresh with address
the control signal CAS, or W, whi-
transfer
chever becomes active as the last.
Low power dissipation
The selection of one or more
Power supply voltage 5 V
memory circuits can be made via the
Package PDIP18 (300 mil)
RAS input.
Operating temperature range
0 to 70 擄C
Quality assessment according to
Read-Write-Control
CECC 90000, CECC 90100 and The choice between Read or Write
CECC 90112
cycle is made at the W input. HIGH
at the W input causes a Read cycle,
meanwhile LOW leads to a Write
Description
cycle.
Both CAS-controlled and W-control-
Addressing
The UD61464 is a dynamic random led Write cycles are possible with
access memory organized 65536 activated RAS signal.
words by 4 bits.
UD61464
64K x 4 DRAM
Data Output Control
The usual state of the data output is
the High-Z state. Whenever CAS is
inactive (HIGH), Q will float (High-Z).
Thus, CAS functions as data output
control.
After access time, in case of a Read
cycle, the output is activated, and it
contains the logic 鈥?鈥?or 鈥?鈥?
If the memory cycle is a Read,
Read-Write or a Write cycle (W-con-
trolled), Q changes from High-Z
state to the active state (鈥?鈥?or 鈥?鈥?.
After access time, the contents of
the selected cell will be available,
with the exception of the Write cycle.
The output remains active until CAS
becomes inactive, irrespective of
RAS becoming inactive or not. The
memory cycle being a Write cycle
(CAS-controlled), the data output
keeps its High-Z state throughout
the whole cycle. This configuration
makes Q fully controllable by the
user merely through the timing of W.
Through storaging the data on out-
put, they remain valid from the end
of access time until the start of
another cycle.
Features
F
F
F
F
F
F
F
F
F
F
F
F
Pin Configuration
Pin Description
(OE)
G
DQ0
DQ1
1
2
3
4
5
6
7
8
9
18
17
16
15
VSS
DQ3
CAS
DQ2
A6
A3
A4
A5
A7
Signal Name
A0 - A7
DQ0 - DQ3
W
RAS
G
VCC
VSS
CAS
Signal Description
Address Inputs
Data In/Out
Read, Write Control
Row Address Strobe
Output Enable
Power Supply Voltage
Ground
Column Address Strobe
(WE)
W
RAS
A0
A2
A1
VCC
PDIP
14
13
12
11
10
Top View
December 12, 1997
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