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Fully Programmable Reset Threshold
Fully Programmable Reset Period
Fully Programmable Watchdog Period
2% Accurate Reset Threshold
VDD Can Go as Low as 2V
18碌A(chǔ) Maximum IDD
Reset Valid Down to 1V
DESCRIPTION
The UCC3946 is designed to provide accurate microprocessor supervi-
sion, including reset and watchdog functions. During power up, the IC
asserts a reset signal RES with VDD as low as 1V. The reset signal re-
mains asserted until the VDD voltage rises and remains above the re-
set threshold for the reset period. Both reset threshold and reset period
are programmable by the user. The IC is also resistant to glitches on
the VDD line. Once RES has been deasserted, any drops below the
threshold voltage need to be of certain time duration and voltage mag-
nitude to generate a reset signal. These values are shown in Figure 1.
An I/O line of the microprocessor may be tied to the watchdog input
(WDI) for watchdog functions. If the I/O line is not toggled within a set
watchdog period, programmable by the user, WDO will be asserted.
The watchdog function will be disabled during reset conditions.
The UCC3946 is available in 8-pin SOIC(D), 8-pin DIP (N or J) and
8-pin TSSOP(PW) packages to optimize board space.
BLOCK DIAGRAM
VDD
8
400nA
POWER TO
CIRCUITRY
RP
4
1.235V
RTH
2
.
3
RES
POWER ON RESET
400nA
8-BIT COUNTER
WP
6
A3
A2
100mV
CLR
A1
A0
CLK
1.235V
WATCHDOG TIMING
WDI
7
EDGE DETECT
5
WDO
1
GND
UDG-98001
Note: Pinout represents the 8-pin TSSOP package.
SLUS247B - FEBRUARY 2000