鈥?/div>
Combines PFC and 2
Converter Function
nd
PRELIMINARY
DESCRIPTION
Stage Down
The UCC18500 family provides all of the functions necessary for an ac-
tive power factor corrected preregulator and a second stage DC-to-DC
converter. The controller achieves near-unity power factor by shaping
the AC input line current waveform to correspond to the AC input line
voltage using average current mode control. The DC-to-DC converter
uses peak current mode control to perform the step down power con-
version.
The PFC stage is leading edge modulated while the second stage is
trailing edge synchronized to allow for minimum overlap between the
boost and PWM switches. This reduces ripple current in the bulk output
capacitor.
In order to operate with a three to one range of input line voltages, a
line feedforward (V
FF
) in used to keep input power constant with vary-
ing input voltage. Generation of V
FF
is done using I
AC
in conjunction
with an external single pole filter. This not only reduces external parts
count, but avoids the use of high voltage components offering a lower
cost solution. The multiplier then divides the line current by the square
of V
FF
.
(continued)
鈥?/div>
Controls Boost PWM to Near-unity Power
Factor
鈥?/div>
Accurate Power Limiting
鈥?/div>
Average Current Mode Control in PFC
Stage
鈥?/div>
Peak Current Mode Control in Second
Stage
鈥?/div>
Programmable Oscillator
鈥?/div>
Leading Edge/Trailing Edge Modulation
for Reduced Output Ripple Using
SmartSync鈩?/div>
鈥?/div>
Low Startup Supply Current
鈥?/div>
Synchronized Second Stage Start-up,
with Programmable Soft-start
鈥?/div>
Programmable Second Stage Shut-down
BLOCK DIAGRAM
VERR ISENSE2
7
8
SS2
13
SECOND STAGE
SOFT START
6.75V
OVP/ENBL
4
UVLO2
1.5V
鈥?/div>
+
8.0V
VAOUT
1
VOLTAGE
ERROR AMP
VSENSE
3
鈥?/div>
+
7.5V
VFF
19
(V
FF
)
2
MIRROR
2:1
IAC
MOUT
18
17
16
ISENSE1
15
CAOUT
2
RT
5
CT
UDG-98189
VCC
9
GND
6
7.5V
REFERENCE
UVLO
16V/10
VCC
20
VREF
ENABLE
I
LIMIT
+
鈥?/div>
0.25V
鈥?/div>
+
ZERO
POWER
PWM
CLK2
PFCOVP
1.5V 1.3V
R
R
S
10
Q
GT2
梅
X
MULT
鈥?/div>
+
CURRENT AMP
鈥?/div>
PWM
+
OSC
CLK1
CLK2
CLK2
CLK1
OSCILLATOR
I
LIMIT
S
Q
PWM
LATCH
R
X
VCC
12
GT1
R
11
PWRGND
鈥?/div>
+
14
PKLMT
SLUS419 - AUGUST 1999
UCC18500相關(guān)型號PDF文件下載
-
型號
版本
描述
廠商
下載
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