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UC3823AJ Datasheet

  • UC3823AJ

  • Analog IC

  • 9頁

  • ETC

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application
INFO
available
UC1823A,B/1825A,B
UC2823A,B/2825A,B
UC3823A,B/3825A,B
High Speed PWM Controller
FEATURES
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Improved versions of the
UC3823/UC3825 PWMs
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Compatible with Voltage or
Current-Mode Topologies
鈥?/div>
Practical Operation at Switching
Frequencies to 1MHz
鈥?/div>
50ns Propagation Delay to Output
鈥?/div>
High Current Dual Totem Pole
Outputs (2A Peak)
鈥?/div>
Trimmed Oscillator Discharge Current
鈥?/div>
Low 100碌A(chǔ) Startup Current
鈥?/div>
Pulse-by-Pulse Current Limiting
Comparator
鈥?/div>
Latched Overcurrent Comparator With
Full Cycle Restart
DESCRIPTION
The UC3823A & B and the UC3825A & B family of PWM control ICs are
improved versions of the standard UC3823 & UC3825 family. Performance
enhancements have been made to several of the circuit blocks. Error ampli-
fier gain bandwidth product is 12MHz while input offset voltage is 2mV. Cur-
rent limit threshold is guaranteed to a tolerance of 5%. Oscillator discharge
current is specified at 10mA for accurate dead time control. Frequency ac-
curacy is improved to 6%. Startup supply current, typically 100碌A(chǔ), is ideal
for off-line applications. The output drivers are redesigned to actively sink
current during UVLO at no expense to the startup current specification. In
addition each output is capable of 2A peak currents during transitions.
Functional improvements have also been implemented in this family. The
UC3825 shutdown comparator is now a high-speed overcurrent comparator
with a threshold of 1.2V. The overcurrent comparator sets a latch that en-
sures full discharge of the soft start capacitor before allowing a restart.
While the fault latch is set, the outputs are in the low state. In the event of
continuous faults, the soft start capacitor is fully charged before discharge
to insure that the fault frequency does not exceed the designed soft start
period. The UC3825 Clock pin has become CLK/LEB. This pin combines
the functions of clock output and leading edge blanking adjustment and has
been buffered for easier interfacing.
(continued)
BLOCK DIAGRAM
* Note: 1823A,B Version Toggles Q and Q are always low
UDG-95101
SLUS334A - AUGUST 1995 - REVISED NOVEMBER 2000

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