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U630H16D1K45G1 Datasheet

  • U630H16D1K45G1

  • HARDSTORE 2K X 8 NVSRAM

  • 14頁(yè)

  • ETC

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U630H16
HardStore
2K x 8 nvSRAM
Features
High-performance CMOS nonvo-
latile static RAM 2048 x 8 bits
25, 35 and 45 ns Access Times
12, 20 and 25 ns Output Enable
Access Times
Hardware STORE Initiation
(STORE Cycle Time < 10 ms)
Automatic STORE Timing
10
6
STORE cycles to EEPROM
100 years data retention in
EEPROM
Automatic RECALL on Power Up
Hardware RECALL Initiation
(RECALL Cycle Time < 20
碌s)
Unlimited RECALL cycles from
EEPROM
Unlimited Read and Write to
SRAM
Single 5 V
鹵
10 % Operation
Operating temperature ranges:
0 to 70
擄C
-40 to 85
擄C
-40 to 125 擄C (only 35 ns)
QS 9000 Quality Standard
ESD protection > 2000 V
(MIL STD 883C M3015.7-HBM)
RoHS compliance and Pb- free
Packages: SOP28 (300 mil),
PDIP28 (300/600 mil)
Description
The U630H16 has two separate
modes of operation: SRAM mode
and nonvolatile mode, determined
by the state of the NE pin.
In SRAM mode, the memory ope-
rates as an ordinary static RAM. In
nonvolatile operation, data is trans-
ferred in parallel from SRAM to
EEPROM or from EEPROM to
SRAM. In this mode SRAM
functions are disabled.
The U630H16 is a fast static RAM
(25, 35, 45 ns), with a nonvolatile
electrically
erasable
PROM
(EEPROM) element incorporated
in each static memory cell. The
SRAM can be read and written an
unlimited number of times, while
independent nonvolatile data resi-
des in EEPROM. Data transfers
from the SRAM to the EEPROM
(the STORE operation), or from the
EEPROM to the SRAM (the
RECALL operation) are initiated
through the state of the NE pin.
The U630H16 combines the high
performance and ease of use of a
fast SRAM with nonvolatile data
integrity.
Once a STORE cycle is initiated,
further input or output are disabled
until the cycle is completed.
Internally, RECALL is a two step
procedure. First, the SRAM data is
cleared and second, the nonvola-
tile information is transferred into
the SRAM cells.
The RECALL operation in no way
alters the data in the EEPROM
cells. The nonvolatile data can be
recalled an unlimited number of
times.
Pin Configuration
NE
n.c.
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
VSS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
VCC
W
n.c.
A8
A9
n.c.
G
A10
E
DQ7
DQ6
DQ5
DQ4
DQ3
Pin Description
Signal Name
A0 - A10
DQ0 - DQ7
E
G
W
NE
VCC
VSS
Signal Description
Address Inputs
Data In/Out
Chip Enable
Output Enable
Write Enable
Nonvolatile Enable
Power Supply Voltage
Ground
PDIP
22
SOP
21
20
19
18
17
16
15
Top View
April 7, 2005
1

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