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U62H256SA55 Datasheet

  • U62H256SA55

  • x8 SRAM

  • 124.67KB

  • 9頁

  • ETC

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U62H256S
Automotive Fast 32K x 8 SRAM
Features
Description
The U62H256S is a static RAM
manufactured using a CMOS pro-
cess technology with the following
operating modes:
- Read
- Standby
- Write
- Data Retention
The memory array is based on a
MIXMOS cell.
The circuit is activated by the fal-
ling edge of E. The address and
control inputs open simultaneously.
According to the information of W
and G, the data inputs, or outputs,
are active. During the active state
E = L each address change leads
to a new Read or Write cycle. In a
Read cycle, the data outputs are
activated by the falling edge of G,
afterwards the data word will be
available at the outputs DQ0-DQ7.
After the address change, the data
outputs go High-Z until the new
information is available. The data
outputs have no preferred state. If
the memory is driven by CMOS
levels in the active state, and if
there is no change of the address,
data input and control signals W or
G, the operating current (I
O
= 0 mA)
drops to the value of the operating
current in the Standby mode. The
Read cycle is finished by the falling
edge of W, or by the rising edge of
E, respectively.
Data retention is guaranteed down
to 2 V. With the exception of E, all
inputs consist of NOR gates, so
that no pull-up/pull-down resistors
are required.
F
32768 x 8 bit static CMOS RAM
F
35 and 55 ns Access Time
F
Common data inputs and
data outputs
F
Three-state outputs
F
Typ. operating supply current
F
F
F
F
F
F
F
F
F
35 ns: 45mA
55 ns: 30mA
Standby current < 2 mA
TTL/CMOS-compatible
Automatic reduction of power
dissipation in long Read or Write
cycles
Power supply voltage 5 V
Operating temperature range
-40
擄C
to 85
擄C
-40
擄C
to 125
擄C
CECC 90000 Quality Standard
ESD protection > 2000 V
(MIL STD 883C M3015.7)
Latch-up immunity >100 mA
Package:
SOP28 (300 mil)
Pin Configuration
Pin Description
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
VSS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
VCC
W
A13
A8
A9
A11
G
A10
E
DQ7
DQ6
DQ5
DQ4
DQ3
Signal Name
A0 - A14
DQ0 - DQ7
E
G
W
VCC
VSS
Signal Description
Address Inputs
Data In/Out
Chip Enable
Output Enable
Write Enable
Power Supply Voltage
Ground
SOP
21
20
19
18
17
16
15
Top View
March 8, 1999
1

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