U6264B
Standard 8K x 8 SRAM
Features
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8192 x 8 bit static CMOS RAM
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70 ns Access Times
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Common data inputs and
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Description
The U6264B is a static RAM manu-
factured using a CMOS process
technology with the following ope-
rating modes:
- Read
- Standby
- Write
- Data Retention
The memory array is based on a
6-transistor cell.
The circuit is activated by the rising
edge of E2 (at E1 = L), or the falling
edge of E1 (at E2 = H). The
address and control inputs open
simultaneously. According to the
information of W and G, the data
inputs, or outputs, are active. In a
Read cycle, the data outputs are
activated by the falling edge of G,
afterwards the data word read will
be available at the outputs DQ0 -
DQ7. After the address change, the
data outputs go High-Z until the
new read information is available.
The data outputs have no preferred
state. If the memory is driven by
CMOS levels in the active state,
and if there is no change of the
address, data input and control
signals W or G, the operating cur-
rent (at I
O
= 0 mA) drops to the
value of the operating current in the
Standby mode. The Read cycle is
finished by the falling edge of E2 or
W, or by the rising edge of E1,
respectively.
Data retention is guaranteed down
to 2 V. With the exception of E2, all
inputs consist of NOR gates, so
that no pull-up/pull-down resistors
are required. This gate circuit
allows to achieve low power
standby requirements by activation
with TTL-levels too.
If the circuit is inactivated by
E2 = L, the standby current (TTL)
drops to 150
碌A(chǔ)
typ.
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outputs
Three-state outputs
Typ. operating supply current
70 ns: 10 mA
Standby current:
< 2
碌A(chǔ)
at T
a
鈮?/div>
70 擄C
Data retention current at 2 V:
< 1
碌A(chǔ)
at T
a
鈮?/div>
70 擄C
TTL/CMOS-compatible
Automatic reduction of power
dissipation in long Read or Write
cycles
Power supply voltage 5 V
Operating temperature ranges:
0 to 70
擄C
-40 to 85
擄C
-40 to 125 擄C
QS 9000 Quality Standard
ESD protection > 2000 V
(MIL STD 883C M3015.7)
Latch-up immunity > 100 mA
Packages: PDIP28 (600 mil)
SOP28 (330 mil)
Pin Configuration
Pin Description
n.c.
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
VSS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
Signal Name
VCC
W (WE)
E2 (CE2)
A8
A9
A11
G (OE)
A10
E1 (CE1)
DQ7
DQ6
DQ5
DQ4
DQ3
Signal Description
Address Inputs
Data In/Out
Chip Enable 1
Chip Enable 2
Output Enable
Write Enable
Power Supply Voltage
Ground
not connected
A0 - A12
DQ0 - DQ7
E1
E2
G
W
VCC
VSS
n.c.
PDIP
22
SOP
21
20
19
18
17
16
15
Top View
April 20, 2004
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