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U62256ADK10LL Datasheet

  • U62256ADK10LL

  • STANDARD 32K X 8 SRAM

  • 10頁

  • ETC

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U62256A
Standard 32K x 8 SRAM
Features
!
32768x8 bit static CMOS RAM
!
Access times 70 ns, 100 ns
!
Common data inputs and
Description
The U62256A is a static RAM
manufactured using a CMOS pro-
cess technology with the following
operating modes:
- Read
- Standby
- Write
- Data Retention
The memory array is based on a
6-transistor cell.
The circuit is activated by the fal-
ling edge of E. The address and
control inputs open simultaneously.
According to the information of W
and G, the data inputs, or outputs,
are active. In a Read cycle, the
data outputs are activated by the
falling edge of G, afterwards the
data word read will be available at
the outputs DQ0-DQ7. After the
address change, the data outputs
go High-Z until the new information
read is available. The data outputs
have not preferred state.
The Read cycle is finished by the
falling edge of W, or by the rising
edge of E, respectively.
Data retention is guaranteed down
to 2 V. With the exception of E, all
inputs consist of NOR gates, so
that no pull-up/pull-down resistors
are required.
data outputs
!
Three-state outputs
!
Typ. operating supply current
70 ns: 50 mA
100 ns: 40 mA
!
TTL/CMOS-compatible
!
Automatical reduction of power
dissipation in long Read Cycles
!
Power supply voltage 5 V + 10 %
!
Operating temperature ranges
0 to 70 擄C
-40 to 85 擄C
-40 to 125 擄C
!
QS 9000 Quality Standard
!
ESD protection > 2000 V
(MIL STD 883C M3015.7)
!
Latch-up immunity >100 mA
!
Packages: PDIP28 (600 mil)
SOP28 (330 mil)
Pin Configuration
Pin Description
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
VSS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
20
19
18
17
16
15
VCC
W
A13
A8
A9
A11
G
A10
E
DQ7
DQ6
DQ5
DQ4
DQ3
Signal Name
A0 - A14
DQ0 - DQ7
E
G
W
VCC
VSS
Signal Description
Address Inputs
Data In/Out
Chip Enable
Output Enable
Write Enable
Power Supply Voltage
Ground
PDIP
SOP
21
Top View
April 20, 2004
1

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