U2739M
DAB One-Chip Channel- and Source / Data Decoder
Description
The U2739M is an integrated circuit in advanced CMOS
technology for demodulation and decoding of a DAB
signal according to ETS 300 401. The channel decoder
part includes the main features OFDM demodulation and
time and frequency synchronization synchronization
algorithms on OAK DSP core platform. The audio source
decoder supports ISO MPEG 1, 2 layer II half and full
sampling rate. The data decoder part is realized on the
integrated OAK DSP core and includes 2 packet mode
decoders. Several standard interfaces, like I2C/L3, I2S or
RDI are implemented to offer a flexible utilization. The
U2739M offers a user-defined implementation of the time
and frequency synchronization by down-loading the
corresponding software algorithms to the OAK DSP core.
Electrostatic sensitive device.
Observe precautions for handling.
Features
D
Support of mode I, II, III and IV
according to ETS 300 401
D
Time and frequency synchronization with a wide-
range parameter set
D
Digital AFC (frequency tolerance < 0.5 Hz for mode I)
D
Digital AGC with a gain control range of 40 dB
D
On-chip de-interleaver memory for full 1.8 Mbit/s
decoding data rate
D
Optional implementation of user-defined synchronization
strategy by using OAK USE-bootmode
D
Time and frequency synchronization on
DSP OAK core
D
Flexible software configuration (set 1 鈥?(temic
kernel), set 2 鈥?(user extension) concept)
D
D
D
D
Automatic mode detection (AMD)
Generation of receiver status information
Generation of tuner control signals
Generation of pulse width modulated VCXO control
signal
plastic LQFP144 respectively
ceramic QFP144 package for software development
D
FIC interpreter
D
Support of AIC decoding (set 2)
D
Support of Tll decoding and corresponding RDI inser-
tion (set 2)
Audio Source Decoder
D
Plastic TQFP100 package or
D
Power supply 3.3 V, master clock 24.576 MHz
Channel Decoder
D
Audio source decoder ISO MPEG 1, 2 layer II
(ISO/IEC 11172/3)
D
Half (24 kHz according ISO/IEC 13818-3) and full
(48 kHz) sampling rate
D
Demodulation and decoding of up to 64 UEP/EEP
sub-channels
D
I2S and SPDIF output interfaces
D
Programmable fader
D
Programmable DRC
Data Decoder
D
Support of dynamic multipex reconfiguration (DMR)
without mute state
D
Digital Null-Symbol detection (FSYNCH generation)
D
Channel filtering (48 dB)
D
Optional SAW filter equilization
D
Support 2 packet mode decoder on OAK DSP core
D
FIC on-chip memory, acces via MC interface
D
V24/RS232 output
Rev. A1, 02-Nov-98
1 (4)
Preliminary Information
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