鈥?/div>
Self-powered Mode Supporting Seven
Downstream Ports
D
D
D
D
D
D
D
D
D
D
Bus-powered Mode Supporting Four
Downstream Ports
All Downstream Ports Support Full-Speed
and Low-Speed Operations
Power Switching and Overcurrent
Reporting is Provided Per Port or Ganged
Supports Suspend and Resume Operations
Suspend Status Terminal Avaliable for
External Logic Power Down
Supports Custom Vendor ID and Product ID
With External Serial EEPROM
3-State EEPROM Interface to Allow
EEPROM Sharing
Push-Pull Outputs for PWRON Eliminate
the Need for External Pullup Resistors
Noise Filtering on OVRCUR Provides
Immunity to Voltage Spikes
Supports 6-MHz Operation Through Crystal
Input or 48-MHz Input Clock
New Functional Pins Introduced to Reduce
the Board Material Cost
鈥?/div>
3 LED Indicator Control Outputs
Enable Visualized Monitoring of 6
Different Hub/Port Status (HUBCFG,
PORTPWR, PORTDIS)
D
Output Pin Available to Disable
External Pullup Resistor on DP0 for 15
ms After Reset or After Change on
BUSPWR and Enable Easy
Implementation of On-Board Bus/Self
Power Dynamic Switching Circuitry
Available in 48-Pin LQFP
鈥?/div>
Package
鈥?/div>
PT PACKAGE
(TOP VIEW)
MODE
EXTMEM
VCC
XTAL1/CLK48
XTAL2
GND
PORTDIS
PORTPWR
HUBCFG
DP7
DM7
OVRCUR7
48
47
46
45
44
43
42
41
40
39
38
37
SUSPND
DP0PUR
DP0
DM0
GND
RESET
EECLK
EEDATA/GANGED
VCC
BUSPWR
PWRON1
OVRCUR1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
36
35
34
33
32
31
30
29
28
27
26
25
PWRON7
DP6
DM6
OVRCUR6
PWRON6
DP5
DM5
OVRCUR5
PWRON5
DP4
DM4
OVRCUR4
NC 鈥?No internal connection
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
JEDEC descriptor S鈥揚(yáng)QFP鈥揋 for low-profile quad flatpack (LQFP)
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
DM1
DP1
PWRON2
OVRCUR2
DM2
DP2
PWRON3
OVRCUR3
DM3
DP3
PWRON4
GND
Copyright
漏
1997, Texas Instruments Incorporated
POST OFFICE BOX 655303
鈥?/div>
DALLAS, TEXAS 75265
1
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