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TSS902ESAP883 Datasheet

  • TSS902ESAP883

  • VITERBI DECODER|CMOS|QFL|132PIN|CERAMIC

  • 46頁

  • ETC

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TSS902E
Viterbi and Reed鈥揝olomon FEC Decoder
1. Description
Digital communication channels are inherently noisy, making transmission error control essential for reliable
communication at low transmit power.
The TSS902E is a single鈥揷hip Forward Error Correction decoder; it conforms to the MPEG鈥揑I transport layer protocol
specified by ISO/IEC standard and FEC requirements of Digital Video Broadcasting (DVB) specification; its typical
applications are DVB satellites, regenerative multi鈥搈edia transmission satellites and military communications.
The TSS902E capabilities rely on Viterbi and Reed鈥揝olomon decoding algorithms to achieve extremely low bit鈥揺rror
rate (BER) on the transmitted data. Allowing discontinuous data blocks transmission, the TSS902E burst mode feature
is unique.
The component is made of the following blocks:
G
The inner decoder which performs the first level error detection and correction.
This unit is made of a depuncturing block, a Viterbi decoder (k=7) and a synchronization/clock controller.
G
The convolutional deinterleaver, l=12 bytes for RS (204, 188, T=8) configuration.
G
The outer decoder performs the second level error protection, using a Reed Solomon (255, 239) error correcting
process.
G
The descrambler for energy dispersal removal.
G
A micro鈥損rocessor interface to setup the device and monitor the testability functions.
While monitoring the inner Viterbi decoder BER output, the phase and the depuncturing pattern are tuned until the
Viterbi decoder proper alignment is found.
The Viterbi decoder output feeds the deinterleaver and Reed鈥揝olomon decoder synchronization module. Once the
synchronization words have been found, the deinterleaver, the outer Reed鈥揝olomon decoder and the descrambler are
properly aligned.
Each functional block may be by鈥損assed, giving more flexibility to a system designer.
2. Features
2.1. General
G
G
G
G
G
G
G
G
G
G
Compliant with ETS 300 421 for DVB, DVB鈥揝.
Compliant with ISO/IEC鈥揅D 13818鈥? MPEG鈥揑I transport layer protocol.
Input code rate frequency up to 10 MBits/sec at 5V.
On鈥揷hip Bit Error Rate monitoring.
SEU immunity better than 30 MeV/mg/cm
2
Total dose better than 50 Krad (Si).
Supply voltage 3 to 5V.
Power consumption 1W at 5V / 10MHz external clock frequency (code rate 7/8).
0.6
碌m
drawn CMOS, 3 metal layers.
132鈥損in MQFP.
2.2. Viterbi Decoder
G
Selectable code rates
1
/
2
,
2
/
3
,
3
/
4
,
5
/
6
and
7
/
8
or automatic acquisition mode
.
Rev. D
鈥?/div>
April 1999
1

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