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TSPC860XRVZQU66D Datasheet

  • TSPC860XRVZQU66D

  • Integrated Communication Processor

  • 93頁(yè)

  • ATMEL   ATMEL

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Features
鈥?/div>
PowerPC
廬
Single Issue Integer Core
鈥?/div>
Precise Exception Model
鈥?/div>
Extensive System Development Support
鈥?On-chip Watchpoints and Breakpoints
鈥?Program Flow Tracking
鈥?On-chip Emulation (Once) Development Interface
High Performance (Dhrystone 2.1: 52 MIPS at 50 MHz, 3.3V, 1.3 Watts Total Power)
Low Power (< 241 mW at 25 MHz, 2.4V Internal, 3.3V I/O-core, Caches, MMUs, I/O)
MPC8XX PowerPC System Interface, Including a Periodic Interrupt Timer, a Bus
Monitor, and Real-time Clocks
Single Issue, 32-bit Version of the Embedded PowerPC Core (Fully Compatible with
Book 1 of the PowerPC Architecture Definition) with 32 脳 32-bit Fixed Point Registers
鈥?Embedded PowerPC Performs Branch Folding, Branch Prediction with
Conditional Prefetch, without Conditional Execution
鈥?4-Kbyte Data Cache and 4-Kbyte Instruction Cache, Each with an MMU
鈥?Instruction and Data Caches are Two-way, Set Associative, Physical Address,
4 Word Line Burst, Least Recently Used (LRU) Replacement, Lockable On-line
Granularity
鈥?MMUs with 32 Entry TLB, Fully Associative Instruction and Data TLBs
鈥?MMUs Support Multiple Page Sizes of 4 KB, 16 KB, 256 KB, 512 KB and 8 MB;
16 Virtual Address Spaces and 8 Protection Groups
鈥?Advanced On-chip Emulation Debug Mode
Up to 32-bit Data Bus (Dynamic Bus Sizing for 8- and 16-bit)
32 Address Lines
Fully Static Design
V
CC
= +3.3V 鹵 5%
f
max
= 66 MHz
Military Temperature Range: -55擄C < T
C
< +125擄C
P
D
= 0.75 W Typical at 66 MHz
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
Integrated
Communication
Processor
TSPC860
Preliminary
Specification
尾-site
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
Description
The TSPC860 PowerPC QUad Integrated Communication Controller (Power QUICC
廬
)
is a versatile one-chip integrated microprocessor and peripheral combination that can
be used in a variety of controller applications. It particularly excels in communications
and networking systems. The Power QUICC (pronounced 鈥渜uick鈥? can be described
as a PowerPC-based derivative of the TS68EN360 (QUICC
鈩?/div>
).
The CPU on the TSPC860 is a 32-bit PowerPC implementation that incorporates
memory management units (MMUs) and instruction and data caches. The communi-
cations processor module (CPM) of the TS68EN360 QUICC has been enhanced with
the addition of a Two-wire Interface (TWI) compatible with protocols such as I
2
C. Mod-
erate to high digital signal processing (DSP) functionality has been added to the CPM.
The memory controller has been enhanced, enabling the TSPC860 to support any
type of memory, including high performance memories and newer dynamic random
access memories (DRAMs). Overall system functionality is completed with the addi-
tion of a PCMCIA socket controller supporting up to two sockets and a real-time clock.
PBGA 357
ZQ suffix
Rev. 2129B鈥揌IREL鈥?2/04

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