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TSXPC603RMGB/Q12LC Datasheet

  • TSXPC603RMGB/Q12LC

  • MICROPROCESSOR|32-BIT|CMOS|BGA|255PIN|CERAMIC

  • 938.50KB

  • 42頁

  • ETC

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Features
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7.4 SPECint95, 6.1 SPECfp95 @ 300 MHz (estimated)
Superscalar (3 instructions per clock peak)
Dual 16 KB Caches
Selectable Bus Clock
32-bit Compatibility PowerPC Implementation
On Chip Debug Support
P
D
typical = 3.5 Watts (266 MHz), Full Operating Conditions
Nap, Doze and Sleep Modes for Power Savings
Branch Folding
64-bit Data Bus (32-bit Data Bus Option)
4G byte Direct Addressing Range
Pipelined Single/double Precision Float Unit
IEEE 754 Compatible FPU
IEEE P 1149-1 Test Mode (JTAG/C0P)
f
int
max = 300 MHz
f
bus
max = 75 MHz
Compatible CMOS Input / TTL Output
Screening / Quality / Packaging
This product is manufactured in full compliance with:
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CI-CGA 255: MIL-STD-883 class Q or According to ATMEL-Grenoble standards
CBGA 255: Upscreenings based upon ATMEL-Grenoble standards
Full Military Temperature Range (T
c
= -55擄C, T
c
= +125擄C)
IndustriaL Temperature Range (T
c
= -40擄C, T
c
= +110擄C)
Internal // I/O Power Supply = 2.5 鹵 5% // 3.3V 鹵 5%
255 Pin CBGA Package and 255 Pin CBGA with SCI (CI-CGA) Package
PowerPC
603e鈩?RISC
Microprocessor
Family
PID7t-603e
Specification
TSPC603R
Description
The PID7t-603e implementation of PowerPC603e (after named 603r) is a low-power
implementation of reduced instruction set computer (RISC) microprocessors Pow-
erPC錚?family. The 603r implements 32-bit effective addresses, integer data types of
8, 16 and 32 bits, and floating-point data types of 32 and 64 bits.
The 603r is a low-power 2.5/3.3-volt design and provides four software controllable
power-saving modes.
The 603r is a superscalar processor capable of issuing and retiring as many as three
instructions per clock. Instructions can execute out of order for increased perfor-
mance; however, the 603r makes completion appear sequential. The 603r integrates
five execution units and is able to execute five instructions in parallel.
The 603r provides independent on-chip, 16K byte, four-way set-associative, physi-
cally addressed caches for instructions and data and on-chip instruction and data
memory management units (MMUs). The MMUs contain 64-entry, two-way set-asso-
ciative, data and instruction translation look aside buffers that provide support for
demand-paged virtual memory address translation and variable-sized block
translation.
The 603r has a selectable 32 or 64-bit data bus and a 32-bit address bus. The 603r
interface protocol allows multiple masters to complete for system resources through a
central external arbiter. The 603r supports single-beat and burst data transfers for
memory accesses, and supports memory-mapped I/O.
Rev. 2125A鈥?2/01
1

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