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TSB41LV03APFP Datasheet

  • TSB41LV03APFP

  • IEEE 1394a THREE-PORT CABLE TRANSCEIVER/ARBITER

  • 50頁

  • TI

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TSB41LV03A, TSB41LV03AI
IEEE 1394a THREE-PORT CABLE TRANSCEIVER/ARBITER
SLLS364A 鈥?JULY 1999 鈥?REVISED MAY 2000
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Fully Supports Provisions of IEEE
1394-1995 Standard for High Performance
Serial Bus
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and the P1394a Supplement
Fully Interoperable With FireWire鈩?and
i.LINK鈩?Implementation of IEEE Std 1394
Fully Compliant With OpenHCI
Requirements
Provides Three P1394a Fully Compliant
Cable Ports at 100/200/400 Megabits per
Second (Mbits/s)
Full P1394a Support Includes: Connection
Debounce, Arbitrated Short Reset,
Multispeed Concatenation, Arbitration
Acceleration, Fly-By Concatenation, Port
Disable/Suspend/Resume
Extended Resume Signaling for
Compatibility With Legacy DV Devices
Power-Down Features to Conserve Energy
in Battery Powered Applications Include:
Automatic Device Power-Down During
Suspend, Device Power-Down Terminal,
Link Interface Disable via LPS, and Inactive
Ports Powered Down
Ultra Low-Power Sleep Mode
Node Power Class Information Signaling
for System Power Management
Cable Power Presence Monitoring
Cable Ports Monitor Line Conditions for
Active Connection to Remote Node
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Register Bits Give Software Control of
Contender Bit, Power Class bits, Link
Active Control Bit and P1394a Features
Data Interface to Link-Layer Controller
Through 2/4/8 Parallel Lines at 49.152 MHz
Interface to Link Layer Controller Supports
Low Cost TI鈩?Bus-Holder Isolation and
Optional Annex J Electrical Isolation
Interoperable With Link-Layer Controllers
Using 3.3-V and 5-V Supplies
Interoperable With Other Physical Layers
(PHYs) Using 3.3-V and 5-V Supplies
Low Cost 24.576-MHz Crystal Provides
Transmit, Receive Data at 100/200/400
Mbits/s, and Link-Layer Controller Clock at
49.152 MHz
Incoming Data Resynchronized to Local
Clock
Logic Performs System Initialization and
Arbitration Functions
Encode and Decode Functions Included for
Data鈥揝trobe Bit Level Encoding
Separate Cable Bias (TPBIAS) for Each Port
Single 3.3-V Supply Operation
Low Cost High Performance 80-Pin TQFP
(PFP) Thermally Enhanced Package
Direct Drop-In Upgrade for TSB41LV03PFP
description
The TSB41LV03A provides the digital and analog transceiver functions needed to implement a three-port node
in a cable-based IEEE 1394 network. Each cable port incorporates two differential line transceivers. The
transceivers include circuitry to monitor the line conditions as needed for determining connection status, for
initialization and arbitration, and for packet reception and transmission. The TSB41LV03A is designed to
interface with a line layer controller (LLC), such as the TSB12LV21, TSB12LV22, TSB12LV23, TSB12LV31,
TSB12LV41, TSB12LV42 or TSB12LV01A.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
鈥營mplements technology covered by one or more patents of Apple Computer, Incorporated and SGS Thompson, Limited.
i.LINK is a trademark of Sony Corporation
FireWire is a trademark of Apple Computers Incorporated.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright
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2000, Texas Instruments Incorporated
POST OFFICE BOX 655303
鈥?/div>
DALLAS, TEXAS 75265
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TSB41LV03APFP 產(chǎn)品屬性

  • Texas Instruments

  • 緩沖器和線路驅(qū)動器

  • 5 V

  • 3.3 V

  • SMD/SMT

  • HTQFP-80

  • Tray

  • IEEE- 1394a

  • 3

  • 96

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