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TPS56302PWP Datasheet

  • TPS56302PWP

  • DUAL-OUTPUT LOW-INPUT-VOLTAGE DSP POWER SUPPLY CONTROLLER WI...

  • 789.59KB

  • 34頁

  • TI

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TPS56302
DUAL-OUTPUT LOW-INPUT-VOLTAGE
DSP POWER SUPPLY CONTROLLER WITH SEQUENCING
SLVS289 鈥?MARCH 2000
D
D
D
D
D
D
D
D
D
D
PWP PowerPAD鈩?PACKAGE
2.8 V 鈥?5.5 V Input Voltage Range
(TOP VIEW)
Programmable Dual Output Controller
Supports Popular DSP, FPGA and
1
28
DROOP
VID0
Microcontroller Core and I/O Voltages
2
27
VID1
OCP
鈥?Switching Regulator Controls I/O Voltage
SLOWST
3
26
IOUT
鈥?Low Dropout Controller Regulates Core
4
25
PWRGD
VHYST
Voltage
5
24
VSEN鈥揕DO
VREFB
6
23
VSEN鈥揜R
NGATE鈥揕DO
Thermal
Adjustable Slow-Start for Simultaneous
7
22
Pad
ANAGND
INHIBIT
Powerup of Both Outputs
8
21
IOUTLO
BIAS
Power Good Output Monitors Both Outputs
9
20
VLDODRV
HISENSE
Fast Ripple Regulator Reduces Bulk
10
19
CPC1
LOSENSE/LOHIB
Capacitance for Lower System Costs
11
18
V
CC
HIGHDR
12
17
BOOT
CPC2
鹵1.5%
Reference Voltage Tolerance
13
16
BOOTLO
VDRV
Efficiencies Greater Than 90%
14
15
LDWDR
DRVGND
Overvoltage, Undervoltage, and Adjustable
Overcurrent Protection
AVAILABLE VID CODE RANGES
Drives Logic Level N-Channel MOSFETs
Through Entire Input Voltage Range
TPS56300
TPS56302
OUTPUTS
1.3 V TO 3.3 V
1.3 V TO 2.5 V
VOUT鈥揕DO
Evaluation Module TPS56302EVM鈥?63
1.3 V TO 2.5 V
1.3 V TO 3.3 V
VOUT鈥揝witcher
Available
NOTE: See Table 1 for actual VID codes.
description
The high-performance TPS56302 synchronous-buck regulator provides two supply voltages to power the core
and I/O of digital signal processors. The TPS56302 is identical to the TPS56300 except that the reference
voltages of the LDO and switching regulator have been reversed. The switching regulator, using hysteretic
control with droop compensation, supports high current and efficiency for the I/O and other peripheral
components. The LDO controller, suitable for powering the core voltage, drives an external N-channel power
MOSFET and functions as an LDO regulator and as a power distribution switch.
typical design
VI
(2.8 V 鈥?5.5 V)
+
U1
TPS56302PWP
See Table 1
See Table 1
VCC
PWRGD
CPC1
NGATE鈥揕DO
CPC2
VREFB
VSEN鈥揕DO
VHYST
INHIBIT
DROOP
IOUTLO
OCP
HISENSE
IOUT
HIGHDR
SLOWST
VSEN鈥揜R
VID0
VID1
LOSENSE/LOHIB
BOOT
BIAS
BOOTLO
VLDODRV
LOWDR
VDRV
ANAGND
DRVGND
PwrPad
+
VCORE
VI/O
+
+
DSP
Data
Data Bus
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerPAD is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright
漏
2000, Texas Instruments Incorporated
+
PERIPHERAL
POST OFFICE BOX 655303
鈥?/div>
DALLAS, TEXAS 75265
1

TPS56302PWP 產(chǎn)品屬性

  • 50

  • 集成電路 (IC)

  • PMIC - 穩(wěn)壓器 - DC DC 切換控制器

  • -

  • 控制器

  • 2

  • 400kHz

  • 90%

  • 2.8 V ~ 5.5 V

  • 是

  • 無

  • 無

  • 無

  • 無

  • 無

  • 無

  • 無

  • -40°C ~ 125°C

  • 28-SOIC（0.173"，4.40mm 寬）裸露焊盤

  • 管件

  • 296-10942-ND - EVAL MOD FOR TPS56302

  • 296-2477-5

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