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TPIC6C595D Datasheet

  • TPIC6C595D

  • POWER LOGIC 8-BIT SHIFT REGISTER

  • 11頁

  • TI

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TPIC6C595
POWER LOGIC 8-BIT SHIFT REGISTER
SLIS061A 鈥?JULY 1998 鈥?REVISED JULY 1999
D
D
D
D
D
D
D
D
Low r
DS(on)
. . . 7
鈩?/div>
Typ
Avalanche Energy . . . 30 mJ
Eight Power DMOS Transistor Outputs of
100-mA Continuous Current
250-mA Current Limit Capability
ESD Protection . . . 2500 V
Output Clamp Voltage . . . 33 V
Devices Are Cascadable
Low Power Consumption
D OR N PACKAGE
(TOP VIEW)
V
CC
SER IN
DRAIN0
DRAIN1
DRAIN2
DRAIN3
CLR
G
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
GND
SRCK
DRAIN7
DRAIN6
DRAIN5
DRAIN4
RCK
SER OUT
description
The TPIC6C595 is a monolithic, medium-voltage,
low-current power 8-bit shift register designed for
use in systems that require relatively moderate
load power such as LEDs. The device contains a
built-in voltage clamp on the outputs for inductive
transient protection. Power driver applications
include relays, solenoids, and other low-current or
medium-voltage loads.
logic symbol
鈥?/div>
G
RCK
CLR
SRCK
SER IN
8
10
7
15
2
R
EN3
C2
SRG8
C1
1D
2
3
4
DRAIN0
DRAIN1
This device contains an 8-bit serial-in, parallel-out
5
DRAIN2
shift register that feeds an 8-bit D-type storage
6
DRAIN3
register. Data transfers through both the shift and
11
storage registers on the rising edge of the shift
DRAIN4
12
register clock (SRCK) and the register clock
DRAIN5
13
(RCK), respectively. The device transfers data out
DRAIN6
the serial output (SER OUT) port on the rising
14
DRAIN7
2
edge of SRCK. The storage register transfers data
9
SER OUT
to the output buffer when shift register clear (CLR)
is high. When CLR is low, the input shift register is
鈥?This symbol is in accordance with ANSI/IEEE Std 91-1984
cleared. When output enable (G) is held high, all
and IEC Publication 617-12.
data in the output buffers is held low and all drain
outputs are off. When G is held low, data from the storage register is transparent to the output buffers. When
data in the output buffers is low, the DMOS transistor outputs are off. When data is high, the DMOS transistor
outputs have sink-current capability. The SER OUT allows for cascading of the data from the shift register to
additional devices.
This device contains circuits to protect its inputs and outputs against damage due to high static voltages or electrostatic fields. These
circuits have been qualified to protect this device against electrostatic discharges (ESD) of up to 2 kV according to MIL-STD-883C,
Method 3015; however, it is advised that precautions be taken to avoid application of any voltage higher than maximum-rated
voltages to these high-impedance circuits. During storage or handling, the device leads should be shorted together or the device
should be placed in conductive foam. In a circuit, unused inputs should always be connected to an appropriated logic voltage level,
preferably either VCC or ground. Specific guidelines for handling devices of this type are contained in the publication
Guidelines for
Handling Electrostatic-Discharge-Sensitive (ESDS) Devices and Assemblies
available from Texas Instruments.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright
漏
1999, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303
鈥?/div>
DALLAS, TEXAS 75265
1

TPIC6C595D 產(chǎn)品屬性

  • 40

  • 集成電路 (IC)

  • 邏輯 - 移位寄存器

  • TPIC

  • 移位寄存器

  • 標(biāo)準(zhǔn)

  • 1

  • 8

  • 串行至并行

  • 4.5 V ~ 5.5 V

  • -40°C ~ 125°C

  • 表面貼裝

  • 16-SOIC（0.154"，3.90mm 寬）

  • 16-SOIC N

  • 管件

  • 296-2019296-2019-5

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