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TPIC6B259DW Datasheet

  • TPIC6B259DW

  • POWER LOGIC 8-BIT ADDRESSABLE LATCH

  • 11頁(yè)

  • TI

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TPIC6B259
POWER LOGIC 8-BIT ADDRESSABLE LATCH
SLIS030 鈥?APRIL 1994 鈥?REVISED JULY 1995
D
D
D
D
D
D
D
Low r
DS(on)
. . . 5
鈩?/div>
Typical
Avalanche Energy . . . 30 mJ
Eight Power DMOS-Transistor Outputs of
150-mA Continuous Current
500-mA Typical Current-Limiting Capability
Output Clamp Voltage . . . 50 V
Four Distinct Function Modes
Low Power Consumption
DW OR N PACKAGE
(TOP VIEW)
description
This power logic 8-bit addressable latch controls
open-drain DMOS-transistor outputs and is
designed
for
general-purpose
storage
applications in digital systems. Specific uses
include working registers, serial-holding registers,
and decoders or demultiplexers. This is a multi-
functional device capable of storing single-line
data in eight addressable latches and 3-to-8
decoder or demultiplexer with active-low DMOS
outputs.
NC
V
CC
S0
DRAIN0
DRAIN1
DRAIN2
DRAIN3
S1
GND
GND
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
NC
CLR
D
DRAIN7
DRAIN6
DRAIN5
DRAIN4
G
S2
GND
NC 鈥?No internal connection
FUNCTION TABLE
INPUTS
CLR G
H
H
H
L
L
L
H
L
D
H
L
X
H
OUTPUT OF
ADDRESSED
DRAIN
L
H
Qio
L
EACH
OTHER
DRAIN
Qio
Qio
Qio
H
FUNCTION
Addressable
Latch
Memory
8-Line
Four distinct modes of operation are selectable by
L
L L
Demultiplexer
H
H
controlling the clear (CLR) and enable (G) inputs
L
H X
H
H
Clear
as enumerated in the function table. In the
addressable-latch mode, data at the data-in (D)
LATCH SELECTION TABLE
terminal is written into the addressed latch. The
SELECT INPUTS
DRAIN
addressed DMOS-transistor output inverts the
ADDRESSED
S2 S1
S0
data input with all unaddressed DMOS-transistor
L
L
L
0
outputs remaining in their previous states. In the
L
L
H
1
memory mode, all DMOS-transistor outputs
L
H
L
2
L
H
H
remain in their previous states and are unaffected
3
H
L
L
4
by the data or address inputs. To eliminate the
H
L
H
5
possibility of entering erroneous data in the latch,
H
H
L
6
enable G should be held high (inactive) while the
H
H
H
7
address lines are changing. In the 3-to-8 decoding
H = high level, L = low level
or demultiplexing mode, the addressed output is
inverted with respect to the D input and all other
outputs are off. In the clear mode, all outputs are off and unaffected by the address and data inputs. When data
is low for a given output, the DMOS-transistor output is off. When data is high, the DMOS-transistor output has
sink-current capability.
Outputs are low-side, open-drain DMOS transistors with output ratings of 50 V and 150-mA continuous
sink-current capability. Each output provides a 500-mA typical current limit at T
C
= 25擄C. The current limit
decreases as the junction temperature increases for additional device protection.
The TPIC6B259 is characterized for operation over the operating case temperature range of 鈥?40擄C to 125擄C.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright
漏
1997, Texas Instruments Incorporated
POST OFFICE BOX 655303
鈥?/div>
DALLAS, TEXAS 75265
1

TPIC6B259DW 產(chǎn)品屬性

  • 25

  • 集成電路 (IC)

  • 邏輯 - 鎖銷

  • TPIC

  • D 型，可尋址

  • 8:8

  • DMOS

  • 4.5 V ~ 5.5 V

  • 1

  • 150ns

  • -

  • -40°C ~ 125°C

  • 表面貼裝

  • 20-SOIC（0.295"，7.50mm 寬）

  • 20-SOIC

  • 管件

  • 296-9010-5

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