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Typ
Output Short-Circuit Protection
Avalanche Energy . . . 75 mJ
Eight 350-mA DMOS Outputs
50-V Switching Capability
Enhanced Cascading for Multiple Stages
All Registers Cleared With Single Input
Low Power Consumption
NE PACKAGE
(TOP VIEW)
description
The TPIC6A596 is a monolithic, high-voltage,
high-current power logic 8-bit shift register
designed for use in systems that require relatively
high load power. The device contains a built-in
voltage clamp on the outputs for inductive
transient protection. Power driver applications
include relays, solenoids, and other medium-
current or high-voltage loads. Each open-drain
DMOS transistor features an independent
chopping current-limiting circuit to prevent
damage in the case of a short circuit.
DRAIN2
DRAIN3
SRCLR
G
PGND
PGND
RCK
SRCK
DRAIN4
DRAIN5
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
DRAIN1
DRAN0
SER IN
V
CC
PGND
PGND
LGND
SER OUT
DRAIN7
DRAIN6
DW PACKAGE
(TOP VIEW)
This device contains an 8-bit serial-in, parallel-out
8
17
shift register that feeds an 8-bit, D-type storage
16
9
register. Data transfers through both the shift and
10
15
storage registers on the rising edge of the shift-
14
11
register clock (SRCK) and the register clock
12
13
(RCK), respectively. The storage register
transfers data to the output buffer when shift-
register clear (SRCLR) is high. When SRCLR is low, all registers in the device are cleared. When output enable
G is held high, all data in the output buffers is held low and all drain outputs are off. When G is held low, data
from the storage register is transparent to the output buffers. The serial output (SER OUT) is clocked out of the
device on the falling edge of SRCK to provide additional hold time for cascaded applications. This will provide
improved performance for applications where clock signals may be skewed, devices are not located near one
another, or the system must tolerate electromagnetic interference.
Outputs are low-side, open-drain DMOS transistors with output ratings of 50 V and a 350-mA continuous sink
current capability. When data in the output buffers is low, the DMOS-transistor outputs are off. When data is high,
the DMOS-transistor outputs have sink current capability.
Separate power ground (PGND) and logic ground (LGND) terminals are provided to facilitate maximum system
flexibility. All PGND terminals are internally connected, and each PGND terminal must be externally connected
to the power system ground in order to minimize parasitic impedance. A single-point connection between LGND
and PGND must be made externally in a manner that reduces crosstalk between the logic and load circuits.
The TPIC6A596 is offered in a thermally-enhanced dual-in-line (NE) package and a wide-body surface-mount
(DW) package. The TPIC6A596 is characterized for operation over the operating case temperature range of
鈥?40擄C to 125擄C.
DRAIN2
DRAIN3
SRCLR
G
PGND
PGND
PGND
PGND
RCK
SRCK
DRAIN4
DRAIN5
1
2
3
4
5
6
7
24
23
22
21
20
19
18
DRAIN1
DRAIN0
SER IN
V
CC
PGND
PGND
PGND
PGND
LGND
SER OUT
DRAIN7
DRAIN6
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright
漏
2000, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303
鈥?/div>
DALLAS, TEXAS 75265
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