Avalanche Energy . . . 75 mJ
in systems that require relatively high load power.
the outputs for inductive transient protection.
loads.
鈥?/div>
G
RCK
SRCLR
SRCK
9
12
8
13
R
EN3
C2
SRG8
C1
4
3
This device contains an 8-bit serial-in, parallel-out
DRAIN0
2
1D
SER IN
5
shift register that feeds an 8-bit D-type storage
DRAIN1
6
register. Data transfers through both the shift and
DRAIN2
storage registers on the rising edge of the
7
DRAIN3
shift-register clock (SRCK) and the register clock
14
DRAIN4
(RCK) respectively. The storage register transfers
15
data to the output buffer when shift-register clear
DRAIN5
16
(SRCLR) is high. When SRCLR is low, all
DRAIN6
17
registers in the device are cleared. When output
DRAIN7
2
enable (G) is held high, all data in the output
18
SER OUT
buffers is held low and all drain outputs are off.
When G is held low, data from the storage register
鈥?This symbol is in accordance with ANSI/IEEE Std 91-1984
is transparent to the output buffers. The serial
and IEC Publication 617-12.
output (SER OUT) is clocked out of the device on
the falling edge of SRCK to provide additional hold time for cascaded applications. This will provide improved
performance for applications where clock signals may be skewed, devices are not located near one another,
or the system must tolerate electromagnetic interference.
Outputs are low-side, open-drain DMOS transistors with output ratings of 45 V and 250-mA continuous sink
current capability. When data in the output buffers is low, the DMOS-transistor outputs are off. When data is
high, the DMOS-transistor outputs have sink current capability.
Separate power and logic level ground pins are provided to facilitate maximum system flexibility. Pins 1, 10, 11,
and 20 are internally connected, and each pin must be externally connected to the power system ground in order
to minimize parasitic inductance. A single-point connection between pin 19, logic ground (LGND), and pins 1,
10, 11, and 20, power grounds (PGND), must be externally made in a manner that reduces crosstalk between
the logic and load circuits.
The TPIC6596 is characterized for operation over the operating case temperature range of 鈥?40擄C to 125擄C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright
漏
2000, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303
鈥?/div>
DALLAS, TEXAS 75265
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