. . . 1.3
鈩?/div>
Typical
Avalanche Energy . . . 75 mJ
Eight Power DMOS Transistor Outputs of
250-mA Continuous Current
1.5-A Pulsed Current Per Output
Output Clamp Voltage at 45 V
Devices Are Cascadable
Low Power Consumption
DW OR N PACKAGE
(TOP VIEW)
description
The TPIC6595 is a monolithic, high-voltage, high-
current power 8-bit shift register designed for use
in systems that require relatively high load power.
The device contains a built-in voltage clamp on
the outputs for inductive transient protection.
Power driver applications include relays, sole-
noids, and other medium-current or high-voltage
loads.
This device contains an 8-bit serial-in, parallel-out
shift register that feeds an 8-bit D-type storage
register. Data transfers through both the shift and
storage registers on the rising edge of the
shift-register clock (SRCK) and the register clock
(RCK) respectively. The storage register transfers
data to the output buffer when shift-
register clear (SRCLR) is high. When SRCLR is
low, the input shift register is cleared. When output
enable (G) is held high, all data in the output
buffers is held low and all drain outputs are off.
When G is held low, data from the storage register
is transparent to the output buffers. The serial
output (SER OUT) allows for cascading of the
data from the shift register to additional devices.
PGND
V
CC
SER IN
DRAIN0
DRAIN1
DRAIN2
DRAIN3
SRCLR
G
PGND
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
PGND
LGND
SER OUT
DRAIN7
DRAIN6
DRAIN5
DRAIN4
SRCK
RCK
PGND
logic symbol
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G
RCK
SRCLR
SRCK
SER IN
9
12
8
13
3
R
EN3
C2
SRG8
C1
1D
2
4
5
6
7
14
15
16
17
2
18
DRAIN0
DRAIN1
DRAIN2
DRAIN3
DRAIN4
DRAIN5
DRAIN6
DRAIN7
SER OUT
鈥?This symbol is in accordance with ANSI/IEEE Std 91-1984
and IEC Publication 617-12.
Outputs are low-side, open-drain DMOS
transistors with output ratings of 45 V and 250-mA
continuous sink current capability. When data in the output buffers is low, the DMOS-transistor outputs are off.
When data is high, the DMOS-transistor outputs have sink current capability.
Separate power and logic level ground pins are provided to facilitate maximum system flexibility. Pins 1, 10, 11,
and 20 are internally connected, and each pin must be externally connected to the power system ground in order
to minimize parasitic inductance. A single-point connection between pin 19, logic ground (LGND), and pins 1,
10, 11, and 20, power grounds (PGND), must be externally made in a manner that reduces crosstalk between
the logic and load circuits.
The TPIC6595 is characterized for operation over the operating case temperature range of 鈥?40擄C to 125擄C.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright
漏
1995, Texas Instruments Incorporated
POST OFFICE BOX 655303
鈥?/div>
DALLAS, TEXAS 75265
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