. . . 1.3
鈩?/div>
Typical
Avalanche Energy . . . 75 mJ
Eight Power DMOS Transistor Outputs of
250-mA Continuous Current
1.5-A Pulsed Current Per Output
Output Clamp Voltage at 45 V
Four Distinct Function Modes
Low Power Consumption
DW OR N PACKAGE
(TOP VIEW)
description
This power logic 8-bit addressable latch controls
open-drain DMOS transistor outputs and is
designed for general-purpose storage applica-
tions in digital systems. Specific uses include
working registers, serial-holding registers, and
decoders or demultiplexers. This is a multi-
functional device capable of storing single-line
data in eight addressable latches with 3-to-8
decoding or demultiplexing mode active-low
DMOS outputs.
PGND
V
CC
S0
DRAIN0
DRAIN1
DRAIN2
DRAIN3
S1
LGND
PGND
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
PGND
CLR
D
DRAIN7
DRAIN6
DRAIN5
DRAIN4
G
S2
PGND
FUNCTION TABLE
INPUTS
CLR G
H
H
H
L
L
L
L
H
L
L
D
H
L
X
H
L
OUTPUT OF
ADDRESSED
DRAIN
L
H
Qio
L
H
EACH
OTHER
DRAIN
Qio
Qio
Qio
H
H
FUNCTION
Addressable
Latch
Memory
8-Line
Demultiplexer
Four distinct modes of operation are selectable by
L
H X
H
H
Clear
controlling the clear (CLR) and enable (G) inputs
as enumerated in the function table. In the
LATCH SELECTION TABLE
addressable-latch mode, data at the data-in (D)
SELECT INPUTS
DRAIN
terminal is written into the addressed latch. The
ADDRESSED
S2 S1
S0
addressed DMOS transistor output inverts the
L
L
L
0
data input with all unaddressed DMOS-transistor
L
L
H
1
outputs remaining in their previous states. In the
L
H
L
2
memory mode, all DMOS-transistor outputs
L
H
H
3
remain in their previous states and are unaffected
H
L
L
4
by the data or address inputs. To eliminate the
H
L
H
5
possibility of entering erroneous data in the latch,
H
H
L
6
H
H
H
7
enable G should be held high (inactive) while the
address lines are changing. In the 3-to-8 decoding
or demultiplexing mode, the addressed output is inverted with respect to the D input and all other outputs are
high. In the clear mode, all outputs are high and unaffected by the address and data inputs.
Separate power and logic level ground pins are provided to facilitate maximum system flexibility. Pins 1, 10, 11,
and 20 are internally connected, and each pin must be externally connected to the power system ground in order
to minimize parasitic inductance. A single-point connection between pin 9, logic ground (LGND), and pins 1, 10,
11, and 20, power ground (PGND) must be externally made in a manner that reduces crosstalk between the
logic and load circuits.
The TPIC6259 is characterized for operation over the operating case temperature range of 鈥?40擄C to 125擄C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright
漏
1995, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303
POST OFFICE BOX 1443
鈥?/div>
HOUSTON, TEXAS 77251鈥?443
鈥?/div>
DALLAS, TEXAS 75265
1
1
2
3
4
5
6
7
8
9
10
