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TPIC5401 Datasheet

  • TPIC5401

  • H-BRIDGE GATE-PROTECTED POWER DMOS ARRAY

  • 12頁

  • TI

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TPIC5401
H-BRIDGE GATE-PROTECTED
POWER DMOS ARRAY
SLIS024A 鈥?DECEMBER 1993 鈥?REVISED MARCH 1994
D
D
D
Low r
DS(on)
. . . 0.3
鈩?/div>
Typ
High Voltage Output . . . 60 V
Extended ESD Capability . . . 4000 V
D
D
Pulsed Current . . . 10 A Per Channel
Fast Commutation Speed
description
The TPIC5401 is a monolithic gate-protected power DMOS array that consists of four N-channel
enhancement-mode DMOS transistors, two of which are configured with a common source. Each transistor
features integrated high-current zener diodes (Z
CXa
and Z
CXb
) to prevent gate damage in the event that an
overstress condition occurs. These zener diodes also provide up to 4000 V of ESD protection when tested using
the human-body model of a 100-pF capacitor in series with a 1.5-k鈩?resistor.
The TPIC5401 is offered in a 16-pin thermally enhanced dual-in-line (NE) package and a 20-pin wide-body
surface-mount (DW) package and is characterized for operation over the case temperature range of 鈥?40擄C to
125擄C.
NE PACKAGE
(TOP VIEW)
DW PACKAGE
(TOP VIEW)
DRAIN2
SOURCE2/GND
GATE2
GND
GND
GATE4
SOURCE4/GND
DRAIN4
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
SOURCE1
DRAIN1
GATE1
GND
GND
GATE3
DRAIN3
SOURCE3
GND
SOURCE4/GND
GATE4
NC
DRAIN4
SOURCE3
DRAIN3
GATE3
NC
NC
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
SOURCE2/GND
GATE2
NC
NC
DRAIN2
SOURCE1
DRAIN1
GATE1
NC
NC
NC 鈥?No internal connection
schematic
DRAIN1
Q1
GATE1
ZC1b
ZC1a
SOURCE1
DRAIN2
Q2
GATE2
ZC2b
ZC2a
Z2
Z4
ZC4b
ZC4a
GND, SOURCE2, SOURCE4
NOTE: For correct operation, no terminal pin may be taken below GND.
Q4
GATE4
Z1
D1
D2
Z3
ZC3b
ZC3a
SOURCE3
DRAIN4
Q3
GATE3
DRAIN3
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright
漏
1994, Texas Instruments Incorporated
POST OFFICE BOX 655303
鈥?/div>
DALLAS, TEXAS 75265
1

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