. . . 0.25
鈩?/div>
Typ
High Voltage Output . . . 30 V
Pulsed Current . . . 12 A Per Channel
Input Transient and ESD Protection
Compatible With High-Side and Low-Side
Current Sense Resistors
KTR or KTS PACKAGE
(TOP VIEW)
description
The TPIC1310 is a monolithic gate-protected
power DMOS array that consists of six electrically
isolated N-channel enhancement-mode DMOS
transistors configured as a three-half H-bridge.
When suitably heat sunk, the TPIC1310 can drive
motors requiring 2.5 A of phase current. The
DMOS transistors are immune to second break-
down effects and current crowding, problems
often associated with bipolar transistors.
The TPIC1310 is offered in 15-pin through-hole
(KTS) and surface-mount (KTR) PowerFLEX
鈩?/div>
packages and is characterized for operation over
the case temperature range of 鈥?40擄C to 125擄C.
V
DD
OUTA
UGA
LGA
UGB
SUB/GND
SOURCE
OUTB
SOURCE
SUB/GND
LGB
LGC
UGC
OUTC
V
DD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Tab is SUB/GND
schematic
VDD
1, 15
KTR PACKAGE
KTS PACKAGE
Q1
UGA
3
2
OUTA
Q2
UGB
5
8
OUTB
Q3
UG
C
14
OUTC
13
Q4
LGA
4
13 k
Q5
LGB
11
13 k
Q6
LGC
12
13 k
6, 10
SUB/TAB/GND
NOTES: A.
B.
C.
D.
7, 9
SOURCE
Terminals 1 and 15 must be externally connected.
Terminals 6 and 10 must be connected to GND.
Terminals 7 and 9 must be connected to the sense resistor or GND.
No terminal may be taken greater than 0.5 V below GND.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerFLEX is a trademark of Texas Instruments Inc.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright
漏
1997, Texas Instruments Incorporated
POST OFFICE BOX 655303
鈥?/div>
DALLAS, TEXAS 75265
1
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