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TP3410J Datasheet

  • TP3410J

  • TP3410 ISDN Basic Access Echo-Cancelling 2B1Q U Transceiver

  • 32頁(yè)

  • NSC

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TP3410 ISDN Basic Access Echo-Cancelling U Transceiver
September 1994
TP3410 ISDN Basic Access
Echo-Cancelling 2B1Q U Transceiver
General Description
The TP3410 is a complete monolithic transceiver for ISDN
Basic Access data transmission at either end of the U inter-
face Fully compatible with ANSI specification T1 601 it is
built on National鈥檚 advanced double-metal CMOS process
and requires only a single
a
5V power supply A total of
160 kbps full-duplex transmission on a single twisted-pair is
provided with user-accessible channels including 2 鈥楤鈥?/div>
channels each at 64 kbps 1 鈥楧鈥?channel at 16 kbps and an
additional 4 kbps for loop maintenance 12 kbps of band-
width is reserved for framing 2B1Q Line coding is used in
which pairs of binary bits are coded into 1 of 4 quantum
levels for transmission at 80k symbols sec (hence 2 Binary
1 Quaternary) To meet the very demanding specifications
for
k
1 in 10e7 Bit Error Rate even on long loops with cross-
talk the device includes 2 Adaptive Digital Signal Proces-
sors 2 Digital Phase-locked Loops and a controller for auto-
matic activation
The digital interface on the device can be programmed for
compatibility with either of two types of control interface for
chip control and access to all spare bits In one mode a
Microwire serial control interface is used together with a
2B
a
D digital interface which is compatible with the Time-di-
vision Multiplexed format of PCM Combo devices and back-
planes This mode allows independent time-slot assignment
for the 2 B channels and the D channel
Alternatively the GCI (General Circuit Interface) may be se-
lected in which the 2B
a
D data is multiplexed together with
control spare bits and loop maintenance data on 4 pins
Features
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
2 鈥楤鈥?/div>
a
鈥楧鈥?channel 160 kbps transceiver for LT and NT
Meets ANSI T1 601 U S Standard
2B1Q line coding with scrambler descrambler
Range exceeds 18 kft of 26 AWG
l
70 dB adaptive echo-cancellation and equalization
On-chip timing recovery no precision external
components
Direct connection to small line transformer
Automatic activation controller
Selectable digital interface formats
TDM with time-slot assigner up to 64 slots plus
MICROWIRE
TM
control interface
GCI (General Circuit Interface) or
IDL (Inter-chip Digital Link)
Backplane clock DPLL allows free-running XTAL
Elastic data buffers meet Q 502 wander jitter for Slave-
slave mode on PBX Trunk Cards and DLC
EOC and spare bits access with automatic validation
Block error counter
6 loopback test modes
Single
a
5V supply 325 mW active power
20 mW idle mode with line signal 鈥樷€榳ake-up鈥欌€?detector
LT NT-1 NT-2 Trunks U-TE鈥檚 Regenerators etc
Digital Loop Carrier
POTS Pair-Gain Systems
Easy Interface to
Line Card Backplanes
鈥樷€楽鈥欌€?Interface Device
TP3420A
Codec Filter Combos
TP3054 7 and TP3075 6
LAPD Processor
MC68302 HPC16400
HDLC Controller
TP3451
Applications
Y
Y
Y
Y
Combo and TRI-STATE are registered trademarks of National Semiconductor Corporation
MICROWIRE
TM
is a trademark of National Semiconductor Corporation
The General Circuit Interface (G C I ) is an interface specification of the Group-of-Four Euro-
pean Telecommunications Companies
Block Diagram
Note
Pin names show Microwire mode
C
1995 National Semiconductor Corporation
TL H 9151 鈥?1
TL H 9151
RRD-B30M115 Printed in U S A

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