音影先锋亚洲天堂网|电影世界尽头的爱完整版播放|国产 熟女 91|高清无码免费观看欧美日韩|韩国一区二区三区黄色录像|美女亚洲加勒比在线|亚洲综合网 开心五月|7x成人在线入口|成人网站免费日韩毛片区|国产黄片?一级?二级?三级

TMX32C6411AZLZ Datasheet

  • TMX32C6411AZLZ

  • FIXED POINT DIGITAL SIGNAL PROCESSOR

  • 119頁

  • TI

掃碼查看芯片數(shù)據(jù)手冊

上傳產(chǎn)品規(guī)格書

PDF預(yù)覽

TMS320C6411
FIXED POINT DIGITAL SIGNAL PROCESSOR
SPRS196H 鈭?MARCH 2002 鈭?REVISED JULY 2004
D
Low-Cost, High-Performance Fixed-Point
DSP 鈭?TMS320C6411
鈭?3.33-ns Instruction Cycle Time
鈭?300-MHz Clock Rate
鈭?Eight 32-Bit Instructions/Cycle
鈭?Twenty-Eight Operations/Cycle
鈭?2400 MIPS
鈭?Fully Software-Compatible With
TMS320C62x錚?/div>
VelociTI.2錚?Extensions to VelociTI錚?/div>
Advanced Very-Long-Instruction-Word
(VLIW) TMS320C64x錚?DSP Core
鈭?Eight Highly Independent Functional
Units With VelociTI.2錚?Extensions:
鈭?Six ALUs (32-/40-Bit), Each Supports
Single 32-Bit, Dual 16-Bit, or Quad
8-Bit Arithmetic per Clock Cycle
鈭?Two Multipliers Support
Four 16 x 16-Bit Multiplies
(32-Bit Results) per Clock Cycle or
Eight 8 x 8-Bit Multiplies
(16-Bit Results) per Clock Cycle
鈭?Non-Aligned Load-Store Architecture
鈭?64 32-Bit General-Purpose Registers
鈭?Instruction Packing Reduces Code Size
鈭?All Instructions Conditional
Instruction Set Features
鈭?Byte-Addressable (8-/16-/32-/64-Bit Data)
鈭?8-Bit Overflow Protection
鈭?Bit-Field Extract, Set, Clear
鈭?Normalization, Saturation, Bit-Counting
鈭?VelociTI.2錚?Increased Orthogonality
L1/L2 Memory Architecture
鈭?128K-Bit (16K-Byte) L1P Program Cache
(Direct Mapped)
鈭?128K-Bit (16K-Byte) L1D Data Cache
(2-Way Set-Associative)
鈭?2M-Bit (256K-Byte) L2 Unified Mapped
RAM/Cache (Flexible RAM/Cache
Allocation)
32-Bit External Memory Interface (EMIF)
鈭?Glueless Interface to Asynchronous
Memories (SRAM and EPROM) and
Synchronous Memories (SDRAM,
SBSRAM, ZBT SRAM, and FIFO)
鈭?512M-Byte Total Addressable External
Memory Space
D
Enhanced Direct-Memory-Access (EDMA)
D
D
Controller (64 Independent Channels)
Host-Port Interface (HPI)
鈭?User-Configurable Bus Width (32-/16-Bit)
鈭?Access to Entire Memory Map
32-Bit/33-MHz, 3.3-V Peripheral Component
Interconnect (PCI) Master/Slave Interface
Conforms to PCI Specification 2.2
鈭?Access to Entire Memory Map
鈭?Three PCI Bus Address Registers:
Prefetchable Memory
Non-Prefetchable Memory I/O
鈭?Four-Wire Serial EEPROM Interface
鈭?PCI Interrupt Request Under DSP
Program Control
鈭?DSP Interrupt Via PCI I/O Cycle
Two Multichannel Buffered Serial Ports
(McBSPs)
鈭?Direct Interface to T1/E1, MVIP, SCSA
Framers
鈭?ST-Bus-Switching Compatible
鈭?Up to 256 Channels Each
鈭?AC97-Compatible
鈭?Serial Peripheral Interface (SPI)
Compatible (Motorola錚?
Three 32-Bit General-Purpose Timers
Sixteen General-Purpose I/O (GPIO) Pins
鈭?Programmable Interrupt/Event
Generation Modes
Flexible PLL Clock Generator
IEEE-1149.1 (JTAG
鈥?/div>
)
Boundary-Scan-Compatible
532-Pin Ball Grid Array (BGA) Package
(GLZ and ZLZ Suffix), 0.8-mm Ball Pitch
0.13-碌m/6-Level Copper Metal Process
鈭?CMOS Technology
3.3-V I/Os, 1.2-V Internal
D
D
D
D
D
D
D
D
D
D
D
D
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
TMS320C62x, VelociTI.2, VelociTI, and TMS320C64x are trademarks of Texas Instruments.
Motorola is a trademark of Motorola, Inc.
鈥?IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright
錚?/div>
2004, Texas Instruments Incorporated
POST OFFICE BOX 1443
鈥?/div>
HOUSTON, TEXAS 77251鈭?443
1

TMX32C6411AZLZ相關(guān)型號PDF文件下載

掃碼下載APP，
一鍵連接廣大的電子世界。

在線人工客服

買家服務(wù)：
賣家服務(wù)：
技術(shù)客服：

0571-85317607

網(wǎng)站技術(shù)支持

13606545031

客服在線時間周一至周五
9:00-17:30

關(guān)注官方微信號，
第一時間獲取資訊。

建議反饋

聯(lián)系人：

聯(lián)系方式：

按住滑塊，拖拽到最右邊
>>
感謝您向阿庫提出的寶貴意見，您的參與是維庫提升服務(wù)的動力！意見一經(jīng)采納，將有感恩紅包奉上哦！