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TMX320DM6437AZDUA Datasheet

  • TMX320DM6437AZDUA

  • Digital Media Processor

  • 2412.84KB

  • 309頁

  • TI

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TMS320DM6437
Digital Media Processor
SPRS345B 鈥?NOVEMBER 2006 鈥?REVISED MARCH 2007
1 TMS320DM6437 Digital Media Processor
1.1 Features
鈥?/div>
High-Performance Digital Media Processor
(DM6437)
鈥?2.5-, 2.-, 1.67-ns Instruction Cycle Time
鈥?400-, 500-, 600-MHz C64x+鈩?Clock Rate
鈥?Eight 32-Bit C64x+ Instructions/Cycle
鈥?3200, 4000, 4800 MIPS
鈥?Fully Software-Compatible With C64x
鈥?Commercial and Extended Temperature
Ranges
VelociTI.2鈩?Extensions to VelociTI鈩?/div>
Advanced Very-Long-Instruction-Word (VLIW)
TMS320C64x+鈩?DSP Core
鈥?Eight Highly Independent Functional Units
With VelociTI.2 Extensions:
鈥?/div>
Six ALUs (32-/40-Bit), Each Supports
Single 32-Bit, Dual 16-Bit, or Quad 8-Bit
Arithmetic per Clock Cycle
鈥?/div>
Two Multipliers Support Four 16 x 16-Bit
Multiplies (32-Bit Results) per Clock
Cycle or Eight 8 x 8-Bit Multiplies (16-Bit
Results) per Clock Cycle
鈥?Load-Store Architecture With Non-Aligned
Support
鈥?64 32-Bit General-Purpose Registers
鈥?Instruction Packing Reduces Code Size
鈥?All Instructions Conditional
鈥?Additional C64x+鈩?Enhancements
鈥?/div>
Protected Mode Operation
鈥?/div>
Exceptions Support for Error Detection
and Program Redirection
鈥?/div>
Hardware Support for Modulo Loop
Auto-Focus Module Operation
C64x+ Instruction Set Features
鈥?Byte-Addressable (8-/16-/32-/64-Bit Data)
鈥?8-Bit Overflow Protection
鈥?Bit-Field Extract, Set, Clear
鈥?Normalization, Saturation, Bit-Counting
鈥?VelociTI.2 Increased Orthogonality
鈥?C64x+ Extensions
鈥?/div>
Compact 16-bit Instructions
鈥?/div>
Additional Instructions to Support
Complex Multiplies
C64x+ L1/L2 Memory Architecture
鈥?256K-Bit (32K-Byte) L1P Program
RAM/Cache [Flexible Allocation]
鈥?640K-Bit (80K-Byte) L1D Data RAM/Cache
[Flexible Allocation]
鈥?1M-Bit (128K-Byte) L2 Unified Mapped
RAM/Cache [Flexible Allocation]
Supports Little Endian Mode Only
Video Processing Subsystem (VPSS)
鈥?Front End Provides:
鈥?/div>
CCD and CMOS Imager Interface
鈥?/div>
BT.601/BT.656 Digital YCbCr 4:2:2
(8-/16-Bit) Interface
鈥?/div>
Preview Engine for Real-Time Image
Processing
鈥?/div>
Glueless Interface to Common Video
Decoders
鈥?/div>
Histogram Module
鈥?/div>
Auto-Exposure, Auto-White Balance and
Auto-Focus Module
鈥?/div>
Resize Engine
鈥?/div>
Resize Images From 1/4x to 4x
鈥?/div>
Separate Horizontal/Vertical Control
鈥?Back End Provides:
鈥?/div>
Hardware On-Screen Display (OSD)
鈥?/div>
Four 54-MHz DACs for a Combination of
鈥?/div>
Composite NTSC/PAL Video
鈥?/div>
Luma/Chroma Separate Video
(S-video)
鈥?/div>
Component (YPbPr or RGB) Video
(Progressive)
鈥?/div>
Digital Output
鈥?/div>
8-/16-bit YUV or up to 24-Bit RGB
鈥?/div>
HD Resolution
鈥?/div>
Up to 2 Video Windows
External Memory Interfaces (EMIFs)
鈥?32-Bit DDR2 SDRAM Memory Controller
With 256M-Byte Address Space (1.8-V I/O)
鈥?Asynchronous 8-Bit Wide EMIF (EMIFA)
With up to 64M-Byte Address Reach
鈥?/div>
Flash Memory Interfaces
鈥?/div>
NOR (8-Bit-Wide Data)
鈥?/div>
NAND (8-Bit-Wide Data)
Enhanced Direct-Memory-Access (EDMA)
Controller (64 Independent Channels)
Two 64-Bit General-Purpose Timers (Each
Configurable as Two 32-Bit Timers)
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this document.
All trademarks are the property of their respective owners.
PRODUCT PREVIEW information concerns products in the
formative or design phase of development. Characteristic data and
other specifications are design goals. Texas Instruments reserves
the right to change or discontinue these products without notice.
Copyright 漏 2006鈥?007, Texas Instruments Incorporated
PRODUCT PREVIEW
鈥?/div>

TMX320DM6437AZDUA 產(chǎn)品屬性

  • Texas Instruments

  • 開發(fā)板和工具包 - TMS320

  • 1

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