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TMX320C6211PYP167 Datasheet

  • TMX320C6211PYP167

  • FIXED-POINT DIGITAL SIGNAL PROCESSORS

  • 83頁

  • TI

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TMS320C6211, TMS320C6211B
FIXED-POINT DIGITAL SIGNAL PROCESSORS
SPRS073K
鈭?/div>
AUGUST 1998
鈭?/div>
REVISED MARCH 2004
D
Excellent Price/Performance Digital Signal
D
D
D
Processors (DSPs): TMS320C62x錚?/div>
(TMS320C6211 and TMS320C6211B)
鈭?/div>
Eight 32-Bit Instructions/Cycle
鈭?/div>
C6211, C6211B, C6711, and C6711B are
Pin-Compatible
鈭?/div>
150-, 167-MHz Clock Rates
鈭?/div>
6.7-, 6-ns Instruction Cycle Time
鈭?/div>
1200, 1333 MIPS
鈭?/div>
Extended Temperature Device (C6211B)
VelociTI錚?Advanced Very Long Instruction
Word (VLIW) C62x錚?DSP Core (C6211/11B)
鈭?/div>
Eight Highly Independent Functional
Units:
鈭?/div>
Six ALUs (32-/40-Bit)
鈭?/div>
Two 16-Bit Multipliers (32-Bit Results)
鈭?/div>
Load-Store Architecture With 32 32-Bit
General-Purpose Registers
鈭?/div>
Instruction Packing Reduces Code Size
鈭?/div>
All Instructions Conditional
Instruction Set Features
鈭?/div>
Byte-Addressable (8-, 16-, 32-Bit Data)
鈭?/div>
8-Bit Overflow Protection
鈭?/div>
Saturation
鈭?/div>
Bit-Field Extract, Set, Clear
鈭?/div>
Bit-Counting
鈭?/div>
Normalization
L1/L2 Memory Architecture
鈭?/div>
32K-Bit (4K-Byte) L1P Program Cache
(Direct Mapped)
鈭?/div>
32K-Bit (4K-Byte) L1D Data Cache
(2-Way Set-Associative)
鈭?/div>
512K-Bit (64K-Byte) L2 Unified Mapped
RAM/Cache
(Flexible Data/Program Allocation)
D
Device Configuration
D
D
D
D
D
D
D
D
D
D
鈭?/div>
Boot Mode: HPI, 8-, 16-, and 32-Bit ROM
Boot
鈭?/div>
Endianness: Little Endian, Big Endian
32-Bit External Memory Interface (EMIF)
鈭?/div>
Glueless Interface to Asynchronous
Memories: SRAM and EPROM
鈭?/div>
Glueless Interface to Synchronous
Memories: SDRAM and SBSRAM
鈭?/div>
512M-Byte Total Addressable External
Memory Space
Enhanced Direct-Memory-Access (EDMA)
Controller (16 Independent Channels)
16-Bit Host-Port Interface (HPI)
鈭?/div>
Access to Entire Memory Map
Two Multichannel Buffered Serial Ports
(McBSPs)
鈭?/div>
Direct Interface to T1/E1, MVIP, SCSA
Framers
鈭?/div>
ST-Bus-Switching Compatible
鈭?/div>
Up to 256 Channels Each
鈭?/div>
AC97-Compatible
鈭?/div>
Serial-Peripheral-Interface (SPI)
Compatible (Motorola錚?
Two 32-Bit General-Purpose Timers
Flexible Phase-Locked-Loop (PLL) Clock
Generator
IEEE-1149.1 (JTAG
鈥?/div>
)
Boundary-Scan-Compatible
256-Pin Ball Grid Array (BGA) Package
(GFN Suffix)
0.18-碌m/5-Level Metal Process
鈭?/div>
CMOS Technology
3.3-V I/Os, 1.8-V Internal
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
TMS320C62x, VelociTI, and C62x are trademarks of Texas Instruments.
Motorola is a trademark of Motorola, Inc.
All trademarks are the property of their respective owners.
鈥?/div>
IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright
錚?/div>
2004, Texas Instruments Incorporated
POST OFFICE BOX 1443
鈥?/div>
HOUSTON, TEXAS 77251鈭?443
1

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