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TMX320C6204GJC100 Datasheet

  • TMX320C6204GJC100

  • FIXED-POINT DIGITAL SIGNAL PROCESSOR

  • 1074.22KB

  • 70頁

  • TI

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TMS320C6205
FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS106E
鈭?/div>
OCTOBER 1999
鈭?/div>
REVISED MARCH 2004
D
High-Performance Fixed-Point Digital
D
D
D
D
D
D
Signal Processor (DSP)
鈭?/div>
TMS320C6205
鈭?/div>
5-ns Instruction Cycle Time
鈭?/div>
200-MHz Clock Rate
鈭?/div>
Eight 32-Bit Instructions/Cycle
鈭?/div>
1600 MIPS
VelociTI錚?Advanced-Very-Long-Instruction-
Word (VLIW) TMS320C62x錚?DSP Core
鈭?/div>
Eight Highly Independent Functional
Units:
鈭?/div>
Six ALUs (32-/40-Bit)
鈭?/div>
Two 16-Bit Multipliers (32-Bit Result)
鈭?/div>
Load-Store Architecture With 32 32-Bit
General-Purpose Registers
鈭?/div>
Instruction Packing Reduces Code Size
鈭?/div>
All Instructions Conditional
Instruction Set Features
鈭?/div>
Byte-Addressable (8-, 16-, 32-Bit Data)
鈭?/div>
8-Bit Overflow Protection
鈭?/div>
Saturation
鈭?/div>
Bit-Field Extract, Set, Clear
鈭?/div>
Bit-Counting
鈭?/div>
Normalization
1M-Bit On-Chip SRAM
鈭?/div>
512K-Bit Internal Program/Cache
(16K 32-Bit Instructions)
鈭?/div>
512K-Bit Dual-Access Internal Data
(64K Bytes)
鈭?/div>
Organized as Two 32K-Byte Blocks for
Improved Concurrency
32-Bit External Memory Interface (EMIF)
鈭?/div>
Glueless Interface to Synchronous
Memories: SDRAM or SBSRAM
鈭?/div>
Glueless Interface to Asynchronous
Memories: SRAM and EPROM
鈭?/div>
52M-Byte Addressable External Memory
Space
Four-Channel Bootloading
Direct-Memory-Access (DMA) Controller
With an Auxiliary Channel
Flexible Phase-Locked-Loop (PLL) Clock
Generator
D
32-Bit/33-MHz
D
D
D
D
D
D
Peripheral
Component
Interconnect (PCI) Master/Slave Interface
Conforms to:
PCI Specification 2.2
Power Management Interface 1.1
Meets Requirements of PC99
鈭?/div>
PCI Access to All On-Chip RAM,
Peripherals, and External Memory
(via EMIF)
鈭?/div>
Four 8-Deep x 32-Wide FIFOs for
Efficient PCI Bus Data Transfer
鈭?/div>
3.3/5-V PCI Operation
鈭?/div>
Three PCI Bus Address Registers:
Prefetchable Memory
Non-Prefetchable Memory I/O
鈭?/div>
Supports 4-Wire Serial EEPROM
Interface
鈭?/div>
PCI Interrupt Request Under DSP
Program Control
鈭?/div>
DSP Interrupt Via PCI I/O Cycle
Two Multichannel Buffered Serial Ports
(McBSPs)
鈭?/div>
Direct Interface to T1/E1, MVIP, SCSA
Framers
鈭?/div>
ST-Bus-Switching Compatible
鈭?/div>
Up to 256 Channels Each
鈭?/div>
AC97-Compatible
鈭?/div>
Serial-Peripheral-Interface (SPI)
Compatible (Motorola錚?
Two 32-Bit General-Purpose Timers
IEEE-1149.1 (JTAG
鈥?/div>
)
Boundary-Scan-Compatible
288-Pin MicroStar BGA錚?Package
(GHK Suffix)
0.15-碌m/5-Level Metal Process
鈭?/div>
CMOS Technology
3.3-V I/Os, 1.5-V Internal, 5-V Voltage
Tolerance for PCI I/O Pins
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
VelociTI, TMS320C62x, and MicroStar BGA are trademarks of Texas Instruments.
Motorola is a trademark of Motorola, Inc.
鈥?/div>
IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright
錚?/div>
2004, Texas Instruments Incorporated
POST OFFICE BOX 1443
鈥?/div>
HOUSTON, TEXAS 77251鈭?443
1

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