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TMS626812A Datasheet

  • TMS626812A

  • 1048576 BY 8-BIT BY 2-BANK SYNCHRONOUS DYNAMIC RANDOM-ACCESS...

  • 565.98KB

  • 40頁

  • TI

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TMS626812
1048576 BY 8-BIT BY 2-BANK
SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORY
SMOS687A 鈥揓ULY 1996 鈥?REVISED APRIL 1997
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Organization . . . 1M
脳
8
脳
2 Banks
3.3-V Power Supply (鹵 10% Tolerance)
Two Banks for On-Chip Interleaving
(Gapless Accesses)
High Bandwidth 鈥?Up to 83-MHz Data Rates
CAS Latency Programmable to 2 or 3
Cycles From Column-Address Entry
Burst Sequence Programmable to Serial or
Interleave
Burst Length Programmable to 1, 2, 4, or 8
Chip Select and Clock Enable for
Enhanced-System Interfacing
Cycle-by-Cycle DQ-Bus Mask Capability
Auto-Refresh and Self-Refresh Capability
4K Refresh (Total for Both Banks)
High-Speed, Low-Noise Low-Voltage TTL
(LVTTL) Interface
Power-Down Mode
Compatible With JEDEC Standards
Pipeline Architecture
Temperature Ranges
Operating, 0擄C to 70擄C
Storage, 鈥?55擄C to 150擄C
Performance Ranges:
SYNCHRONOUS
CLOCK CYCLE
TIME
tCK2
tCK3
(CL = 3) (CL = 2)
ACCESS TIME
CLOCK TO
OUTPUT
tCK2
tCK3
(CL = 3) (CL = 2)
9 ns
9 ns
9 ns
10 ns
REFRESH
INTERVAL
DGE PACKAGE
( TOP VIEW )
V
CC
DQ0
V
SSQ
DQ1
V
CCQ
DQ2
V
SSQ
DQ3
V
CCQ
NC
NC
W
CAS
RAS
CS
A11
A10
A0
A1
A2
A3
V
CC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
V
SS
DQ7
V
SSQ
DQ6
V
CCQ
DQ5
V
SSQ
DQ4
V
CCQ
NC
NC
DQM
CLK
CKE
NC
A9
A8
A7
A6
A5
A4
V
SS
PIN NOMENCLATURE
A0 鈥?A10 Address Inputs
A0 鈥?A10 Row Addresses
A0 鈥?A8 Column Addresses
A10 Automatic-Precharge Select
A11
Bank Select
Column-Address Strobe
CAS
CKE
Clock Enable
CLK
System Clock
Chip Select
CS
DQ0 鈥?DQ7
SDRAM Data Input / Output
DQM
Data / Output Mask Enable
NC
No External Connect
Row-Address Strobe
RAS
VCC
Power Supply (3.3-V Typ)
VCCQ
Power Supply for Output Drivers (3.3-V Typ)
VSS
Ground
VSSQ
Ground for Output Drivers
Write Enable
W
鈥?26812-12A鈥?/div>
鈥?26812-12
12 ns
12 ns
15 ns
18 ns
64 ms
64 ms
鈥?鈥?2A speed device is supported only at 鈥?/+10% VCC
description
The TMS626812 is a high-speed 16 777 216-bit
synchronous dynamic random access memory
(SDRAM) device organized as two banks of
1 048 576 words with eight bits per word.
All inputs and outputs of the TMS626812 series
are compatible with the LVTTL interface.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright
漏
1997, Texas Instruments Incorporated
POST OFFICE BOX 1443
鈥?/div>
HOUSTON, TEXAS 77251鈥?443
1

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    4 194 304 BY 4-BIT/2 097 152 BY 8-BIT/1 048 576 BY 16-BIT BY...
  • 英文版
    524288 BY 16-BIT BY 2-BANK SYNCHRONOUS DYNAMIC RANDOM-ACCESS...
    TI [Texas Instr...
  • 英文版
    1048576 BY 8-BIT BY 2-BANK SYNCHRONOUS DYNAMIC RANDOM-ACCESS...
    TI
  • 英文版
    1048576 BY 8-BIT BY 2-BANK SYNCHRONOUS DYNAMIC RANDOM-ACCESS...
    TI [Texas Instr...
  • 英文版
    1,048,576 BY 8-BIT BY 2-BANK SYNCHRONOUS DYNAMIC RANDOM-ACCE...
    TI [Texas Instr...
  • 英文版
    4 194 304 BY 4-BIT/2 097 152 BY 8-BIT/1 048 576 BY 16-BIT BY...
    TI
  • 英文版
    4 194 304 BY 4-BIT/2 097 152 BY 8-BIT/1 048 576 BY 16-BIT BY...
    TI [Texas ...
  • 英文版
    4 194 304 BY 4-BIT/2 097 152 BY 8-BIT/1 048 576 BY 16-BIT BY...
    TI
  • 英文版
    4 194 304 BY 4-BIT/2 097 152 BY 8-BIT/1 048 576 BY 16-BIT BY...
    TI [Texas ...
  • 英文版
    4 194 304 BY 4-BIT/2 097 152 BY 8-BIT/1 048 576 BY 16-BIT BY...
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    4 194 304 BY 4-BIT/2 097 152 BY 8-BIT/1 048 576 BY 16-BIT BY...
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