TMS470R1A288 Datasheet

IC型號：
TMS470R1A288
PDF描述：
16/32-Bit RISC Flash Microcontroller
文件大?。?/label>
540.67KB
PDF頁數(shù)：
57頁
芯片廠家：
TI

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TMS470R1A288

16/32-Bit RISC Flash Microcontroller

www.ti.com

SPNS106 鈥?SEPTEMBER 2005

FEATURES

鈥?/div>

High-Performance Static CMOS Technology

TMS470R1x 16/32-Bit RISC Core

(ARM7TDMI鈩?

鈥?24-MHz System Clock (48-MHz Pipeline)

鈥?Independent 16/32-Bit Instruction Set

鈥?Open Architecture With Third-Party Support

鈥?Built-In Debug Module

Integrated Memory

鈥?288K-Byte Program Flash

鈥?/div>

Two Banks With 8 Contiguous Sectors

鈥?16K-Byte Static RAM (SRAM)

鈥?Memory Security Module (MSM)

鈥?JTAG Security Module

Operating Features

鈥?Low-Power Modes: STANDBY and HALT

鈥?Industrial Temperature Range

470+ System Module

鈥?32-Bit Address Space Decoding

鈥?Bus Supervision for Memory/Peripherals

鈥?Digital Watchdog (DWD) Timer

鈥?Analog Watchdog (AWD) Timer

鈥?Enhanced Real-Time Interrupt (RTI)

鈥?Interrupt Expansion Module (IEM)

鈥?System Integrity and Failure Detection

鈥?ICE Breaker

Direct Memory Access (DMA) Controller

鈥?32 Control Packets and 16 Channels

Zero-Pin Phase-Locked Loop (ZPLL)-Based

Clock Module With Prescaler

鈥?Multiply-by-8 Internal ZPLL Option

鈥?ZPLL Bypass Mode

Ten Communication Interfaces:

鈥?Two Serial Peripheral Interfaces (SPIs)

鈥?/div>

255 Programmable Baud Rates

鈥?Two Serial Communication Interfaces (SCIs)

鈥?/div>

Selectable Baud Rates

鈥?/div>

Asynchronous/Isosynchronous Modes

鈥?Class II Serial Interface B (C2SIb)

鈥?/div>

Normal 10.4 Kbps and 4X Mode 41.6 Kbps

鈥?Two Standard CAN Controllers (SCC)

鈥?/div>

(1)

鈥?/div>

16-Mailbox Capacity

鈥?/div>

Fully Compliant With CAN Protocol,

Version 2.0B

鈥?Three Inter-Integrated Circuit (I2C) Modules

鈥?/div>

Multi-Master and Slave Interfaces

鈥?/div>

Up to 400 Kbps (Fast Mode)

鈥?/div>

7- and 10-Bit Address Capability

High-End Timer Lite (HET)

鈥?12 Programmable I/O Channels:

鈥?/div>

12 High-Resolution Pins

鈥?High-Resolution Share Feature (XOR)

鈥?High-End Timer RAM

鈥?/div>

64-Instruction Capacity

External Clock Prescale (ECP) Module

鈥?Programmable Low-Frequency External

Clock (CLK)

12-Channel 10-Bit Multi-Buffered ADC

(MibADC)

鈥?64-Word FIFO Buffer

鈥?Single- or Continuous-Conversion Modes

鈥?1.55 碌s Minimum Sample/Conversion Time

鈥?Calibration Mode and Self-Test Features

Flexible Interrupt Handling

Expansion Bus Module (EBM) (PGE only)

鈥?Supports 8- and 16-Bit Expansion Bus

Memory Interface Mappings

鈥?42 I/O Expansion Bus Pins

50 Dedicated General-Purpose I/O (GIO) Pins

and 43 Additional Peripheral I/Os (PGE)

14 Dedicated General-Purpose I/O (GIO) Pins

and 43 Additional Peripheral I/Os (PZ)

16 External Interrupts

On-Chip Scan-Base Emulation Logic, IEEE

Standard 1149.1

(1)

(JTAG) Test-Access Port

144-Pin Plastic Low-Profile Quad Flatpack

(PGE Suffix)

100-Pin Plastic Low-Profile Quad Flatpack (PZ

Suffix)

The test-access port is compatible with the IEEE Standard

1149.1-1990, IEEE Standard Test-Access Port and Boundary

Scan Architecture specification. Boundary scan is not

supported on this device.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

ARM7TDMI is a trademark of Advanced RISC Machines Limited (ARM).

All trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

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