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TMS45160 Datasheet

  • TMS45160

  • 262144-WORD BY 16-BIT HIGH-SPEED DYNAMIC RANDOM-ACCESS MEMOR...

  • 354.36KB

  • 23頁

  • TI

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TMS45160, TMS45160P
262144-WORD BY 16-BIT HIGH-SPEED
DYNAMIC RANDOM-ACCESS MEMORIES
SMHS160D 鈥?AUGUST 1992 鈥?REVISED JUNE 1995
D
D
D
This data sheet is applicable to all TMS45160/Ps
symbolized with Revision 鈥淒鈥?and subsequent
revisions as described on page 21.
Organization . . . 262144
脳
16
5-V Supply (鹵10% Tolerance)
Performance Ranges:
ACCESS ACCESS ACCESS READ OR
TIME
TIME
TIME
WRITE
tRAC
tCAC
tAA
CYCLE
MAX
MAX
MAX
MIN
60 ns
15 ns
30 ns
110 ns
70 ns
20 ns
35 ns
130 ns
80 ns
20 ns
40 ns
150 ns
DZ PACKAGE
( TOP VIEW )
DGE PACKAGE
( TOP VIEW )
D
D
D
D
D
D
D
D
D
D
鈥?5160/P-60
鈥?5160/P-70
鈥?5160/P-80
Enhanced-Page-Mode Operation With
xCAS-Before-RAS (xCBR) Refresh
Long Refresh Period
512-Cycle Refresh in 8 ms (Max)
64 ms Max for Low Power With
Self-Refresh Version ( TMS45160P)
3-State Unlatched Output
Low Power Dissipation
Texas Instruments EPIC鈩?CMOS Process
All Inputs, Outputs, and Clocks Are TTL
Compatible
High-Reliability, 40-Lead, 400-Mil-Wide
Plastic Surface-Mount (SOJ) Package and
40/44-Lead Thin Small-Outline Package
( TSOP)
Operating Free-Air Temperature Range
0擄C to 70擄C
Low Power With Self-Refresh Version
Upper and Lower Byte Control During Read
and Write Operations
V
CC
DQ0
DQ1
DQ2
DQ3
V
CC
DQ4
DQ5
DQ6
DQ7
NC
NC
W
RAS
NC
A0
A1
A2
A3
V
CC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
V
SS
DQ15
DQ14
DQ13
DQ12
V
SS
DQ11
DQ10
DQ9
DQ8
NC
LCAS
UCAS
OE
A8
A7
A6
A5
A4
V
SS
V
CC
DQ0
DQ1
DQ2
DQ3
V
CC
DQ4
DQ5
DQ6
DQ7
1
2
3
4
5
6
7
8
9
10
44
43
42
41
40
39
38
37
36
35
V
SS
DQ15
DQ14
DQ13
DQ12
V
SS
DQ11
DQ10
DQ9
DQ8
NC
NC
W
RAS
NC
A0
A1
A2
A3
V
CC
13
14
15
16
17
18
19
20
21
22
32
31
30
29
28
27
26
25
24
23
NC
LCAS
UCAS
OE
A8
A7
A6
A5
A4
V
SS
PIN NOMENCLATURE
A0 鈥?A8
DQ0 鈥?DQ15
LCAS
NC
OE
RAS
UCAS
VCC
VSS
W
Address Inputs
Data In / Data Out
Lower Column-Address Strobe
No Internal Connection
Output Enable
Row-Address Strobe
Upper Column-Address Strobe
5-V Supply
Ground
Write Enable
description
The TMS45160 series are high-speed, 4 194 304-bit dynamic random-access memories organized as 262 144
words of 16 bits each. The TMS45160P series are high-speed, low-power, self-refresh 4 194 304-bit dynamic
random-access memories organized as 262 144 words of 16 bits each. They employ state-of-the-art EPIC
鈩?/div>
( Enhanced Performance Implanted CMOS) technology for high performance, reliability, and low power at low
cost.
These devices feature maximum RAS access times of 60 ns, 70 ns, and 80 ns. Maximum power dissipation
is as low as 770 mW operating and 11 mW standby on 80-ns devices. All inputs and outputs, including clocks,
are compatible with Series 74 TTL. All addresses and data-in lines are latched on chip to simplify system design.
Data out is unlatched to allow greater system flexibility.
The TMS45160 and TMS45160P are each offered in a 40-lead plastic surface-mount SOJ package ( DZ suffix)
and a 40/44-lead plastic surface-mount small-outline ( TSOP) package ( DGE suffix). These packages are
characterized for operation from 0擄C to 70擄C.
EPIC is a trademark of Texas Instruments Incorporated.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright
漏
1995, Texas Instruments Incorporated
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251鈥?443
鈥?/div>
鈥?/div>
1

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